Commit graph

95242 commits

Author SHA1 Message Date
Kenneth Graunke
081c54099c i965: Delete update_renderbuffer_surface flags.
We don't need yet another set of flags.  The function already has access
to both brw and the unit, so it can check brw->draw_aux_buffer_disabled
itself in one line of code.  The layered flag was only used to assert
that Gen4-5 doesn't do layered rendering, which isn't that useful.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-08-23 11:55:17 -07:00
Kenneth Graunke
f70e0f52c9 i965: Make brw_update_renderbuffer_surface static.
Also rename it to gen6_update_renderbuffer_surface, as this is the
function for Gen6+.  Having functions named "brw_*" and "gen4_*"
is confusing...if we're using gens, let's stick with those.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-08-23 11:55:17 -07:00
Kenneth Graunke
b96313c0e1 i965: Drop BRW_NEW_BLORP from SURFACE_STATE setup code.
BLORP invalidates the binding tables, but it doesn't destroy any of the
existing SURFACE_STATE entries in the statebuffer.  We can reuse those.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-23 11:55:17 -07:00
Kenneth Graunke
54c41af0aa i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.
When changing fast clear colors, we need to emit new SURFACE_STATE
with the updated color at the next draw call.

Most things work today because the atoms that handle SURFACE_STATE
for images (mutable images, textures, render targets) also listen to
BRW_NEW_BLORP, causing us to re-emit these on every BLORP operation.
However, this is overkill - most BLORP operations don't require us
to re-emit SURFACE_STATE.

One case where this is broken today is a fast clear to a different
color followed by a non-coherent framebuffer fetch.  The renderbuffer
read atom doesn't listen to BRW_NEW_BLORP, and would not get the new
fast clear color.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-23 11:55:17 -07:00
Kenneth Graunke
d0b40e2c87 i965: Drop Gen7+ nonsense from brw_ff_gs.c.
brw_ff_gs.c is about using the geometry shader to implement things
that the fixed function ought to do, but doesn't on old hardware.

Gen7+ does not need this.  We should drop the misleading comment
about Gen7 not using geometry shaders.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-08-23 11:55:17 -07:00
Kenneth Graunke
eaf5b8722b i965: Only set key->flat_shade if COL0/COL1 are written.
This may reduce some recompiles.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-08-23 11:55:17 -07:00
Kenneth Graunke
348929015b i965: Clean up brwNewProgram().
All shader stages do the exact same thing, so we don't need the switch
statement, or the redundant FS case.  I believe these used to be
different before Tim eliminated the (e.g.) brw_vertex_program
subclasses.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-08-23 11:55:17 -07:00
Leo Liu
5ff97f2644 st/va: exclude the buffer reallocation for encode case
Since encoder only support de-interlaced buffers.

v2: move to parameter call to tell dec/enc

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-23 14:51:12 -04:00
Tim Rowley
f0602dc920 swr: limit pipe_draw_info->restart_index usage
Only copy this value when in restart drawing mode.

Eliminates valgrind errors when running trivial programs.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-08-23 11:37:50 -05:00
Samuel Pitoiset
7fb4b6f270 radeonsi: fix wrong assertion in si_init_bindless_descriptors()
Bad mistake, sorry.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-08-23 17:13:44 +02:00
Leo Liu
89f75c9483 radeon/video: Return false explicitly for HEVC if not the case
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-23 10:51:14 -04:00
Gwan-gyeong Mun
9649c6acce gallium/docs: Fix the math formula of U2I64
before:
  dst.xy = (uint64_t) src0.x
  dst.zw = (uint64_t) src0.y

after:
  dst.xy = (int64_t) src0.x
  dst.zw = (int64_t) src0.y

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-23 14:09:49 +02:00
Gwan-gyeong Mun
9aabf80ef3 gallium/docs: Add missing word "Not"
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-23 14:09:22 +02:00
Nicolai Hähnle
26996ec3b8 tgsi: store opcode mnemonics in a separate table
They are only used for debug info.

Together with making tgsi_opcode_info::opcode a bitfield, this reduces
the size of tgsi_opcode_info on 64-bit systems from 24 bytes to 4 bytes,
and makes the whole data structure a bit more linker friendly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:57 +02:00
Nicolai Hähnle
438177aa19 gallium: use tgsi_get_opcode_name instead of tgsi_opcode_info::mnemonic
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:55 +02:00
Nicolai Hähnle
2f7c55c23f tgsi: macro-ify the opcodes table
So we can easily re-arrange members of tgsi_opcode_info, and readers of
the code don't have to guess what all the 0s mean.

Mostly done with regex search&replace.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:53 +02:00
Nicolai Hähnle
48ef0a1ee4 tgsi: remove post_indent from some 64-bit opcodes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:51 +02:00
Nicolai Hähnle
3f433e927c tgsi: reduce tgsi_opcode_info::pre_dedent and post_indent to 1 bit
It's not clear why they were ever 2 bits to begin with. Perhaps
the original intent was to use signed values, but that doesn't
seem to have ever been the case in master.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:47 +02:00
Nicolai Hähnle
83c5d12d9d gallium/radeon: fix saving multi-part command streams
Use the correct type to fix pointer arithmetic.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:09 +02:00
Nicolai Hähnle
8937ac9a13 ac/debug: invoke valgrind checks while parsing IBs
Help catch garbage data written into IBs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:07 +02:00
Nicolai Hähnle
c2c3912410 ac/debug: annotate IB dumps with the raw values
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:05 +02:00
Nicolai Hähnle
cfb3824c23 ac/debug: use an explicit getter for fetching words from the IB
Guard against out-of-bounds accesses, and prepare for upcoming changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:03 +02:00
Nicolai Hähnle
6fdd7ba32e radeonsi: update comment describing indices into sctx->descriptors
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:54:01 +02:00
Nicolai Hähnle
556946f801 util: fix valgrind errors when dumping pipe_draw_info
Various index-related fields are only initialized when required, so
they should only be dumped in those cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:53:54 +02:00
Samuel Pitoiset
94cc01105e radeonsi: do not assert when reserving bindless slot 0
When assertions were disabled, the compiler removed
the call to util_idalloc_alloc() and the first allocated
bindless slot was 0 which is invalid per the spec.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-08-23 13:38:56 +02:00
Samuel Pitoiset
f4ec41ecc4 radeonsi: rename some bindless-related helper functions
I think it makes more sense.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:37:07 +02:00
Samuel Pitoiset
9141d13214 radeonsi: minor cleanups in si_make_{texture,image}_handle_resident()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-23 13:37:05 +02:00
Rob Herring
f8e4223728 Android: gallium_dri: pass dri.sym to linker
Pass the dri.sym version script to the linker. This ensures only
explicitly exported symbols are exported and shrinks the library by up
to 60KB.

HAVE_DLADDR also needs to be set so that __driDriverExtensions is defined.

We need to pass "--undefined-version" because the Android build system
sets --no-undefined-version by default and we get an error on
driver specific symbols if those drivers are disabled without the option.

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-08-22 19:02:12 -05:00
Leo Liu
2b025a11be st/va: enable P016 format i.e. reallocate buffer if format changed
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-22 15:13:42 -04:00
Leo Liu
398a299f7b radeon/vcn: enable P016 mode support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-22 15:13:34 -04:00
Leo Liu
df6c087a38 radeon/vcn: correct target buffer pitch calculation
since the way should be as same as UVD

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-22 15:12:19 -04:00
Francisco Jerez
e29ccaac29 anv: Check that in_fence fd is valid before closing it.
Probably harmless, but will overwrite errno with a failure status
code.  Reported by coverity.

CID 1416600: Argument cannot be negative (NEGATIVE_RETURNS)
Fixes: 5c4e4932e0 (anv: Implement support for exporting semaphores as FENCE_FD)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-22 11:56:38 -07:00
Francisco Jerez
7ca124a6a3 anv: Add error handling to setup_empty_execbuf().
The anv_execbuf_add_bo() call can actually fail in practice, which
should cause the QueueSubmit operation to fail.  Reported by Coverity.

CID: 1416606: Unchecked return value (CHECKED_RETURN)
Fixes: 017cdb10cf (anv: Submit a dummy batch when only semaphores are provided.)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-22 11:54:16 -07:00
Marek Olšák
4d807d7fe2 tgsi/scan: fix uses_double
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 18:11:28 +02:00
Marek Olšák
497506ad93 gallium: remove TGSI opcode SCS
use COS+SIN instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2017-08-22 16:42:17 +02:00
Marek Olšák
33efa6416f gallium/u_blitter: don't use boolean, TRUE, FALSE
v2: cherry-picked from the bigger patch series

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Brian Paul <brianp@vmware.com>
2017-08-22 15:21:19 +02:00
Marek Olšák
c7ad07758e gallium/u_simple_shaders: do util_make_layered_clear_vertex_shader differently
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
2017-08-22 15:16:44 +02:00
Marek Olšák
8f75a6f1af gallium/u_blitter: remove get_next_surface_layer callback
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
2017-08-22 15:16:44 +02:00
Samuel Pitoiset
e2f3cfead9 st/glsl_to_tgsi: fix getting the image type for array of structs (again)
We want the type of the field, not of the struct.

This fixes a regression in the following piglit test:
arb_bindless_texture/compiler/images/arrays-of-struct.frag

Fixes: 49d9286a3f ("glsl: stop copying struct and interface member names")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-08-22 13:58:51 +02:00
Marek Olšák
cdaaf66566 gallium: remove TGSI opcode BREAKC
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:33:48 +02:00
Marek Olšák
985e6b5ef9 gallium: remove TGSI opcode XPD
use MUL+MAD+MOV instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
3e2ff8fade gallium: remove TGSI opcode DPH
use DP4 or DP3 + ADD.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
86e6f7a73b gallium: remove TGSI opcode DP2A
use DP3 instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
0bb367830a gallium: remove TGSI_OPCODE_CALLNZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
068c3ad2cb gallium: remove TGSI FENCE opcodes
use MEMBAR instead

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
44716655e6 gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
8dadb07790 radeonsi: emit VGT_REUSE_OFF in the right place
clip_regs aren't marked dirty when writes_viewport_index is changed.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
a6fed63f27 radeonsi: add support for TGSI opcodes DCEIL, DFLR, DROUND, DSSG, DTRUNC
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
addd48194a radeonsi: use a faster version of PK2H
+ 4 piglit regressions, but it's correct accorcing to the GL spec and
performance is more important than piglit.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák
dc2ac03669 radeonsi: don't decompress Z/S if there is no HTILE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00