Commit graph

77366 commits

Author SHA1 Message Date
Chad Versace
0679bef49f anv/meta: Create 8 pipelines for color clears
This prepares for moving the clear ops from the start of the render pass
into each subpass.

Pipeline N will be used to clear color attachment N of the current
subpass. Currently meta color clears still create a throwaway subpass
with exactly one attachment, so currently only pipeline 0 is used.

This is an ugly hack to workaround the compiler's current inability to
dynamically set the render target index in the render target write
message.
2016-01-14 22:53:05 -08:00
Chad Versace
2997b0da4a anv: Allow override of pipeline color attachment count
Add anv_graphics_pipeline_create_info::color_attachment_count. If
non-negative, then it overrides the color attachment count in the
pipeline's subpass. Useful for meta. (All the hacks for meta!)
2016-01-14 22:53:05 -08:00
Chad Versace
13610c03a7 anv/meta: Name the nir shaders
The names appear in debug output.
2016-01-14 22:53:05 -08:00
Chad Versace
6a1a760e3c anv: Move MAX_* defs to top of anv_private.h
Because I need to use MAX_RTS in struct anv_meta_state.
2016-01-14 22:53:05 -08:00
Chad Versace
4c2bafb9bf anv: Define zero() macro
zero(x) memsets x to zero. Eliminates bugs due to errors in memset's
size param.
2016-01-14 22:53:05 -08:00
Chad Versace
f2700d665c anv/meta: Rename emit_load_*_clear funcs
The functions will soon handle clears unrelated to
VK_ATTACHMENT_LOAD_OP_CLEAR, namely vkCmdClearAttachments. So remove
"load" from their name:

    emit_load_color_clear -> emit_color_clear
    emit_load_depthstencil_clear -> emit_depthstencil_clear
2016-01-14 22:53:05 -08:00
Chad Versace
356f952f87 anv/meta: Use anv_cmd_state::attachments for clears
Rewrite anv_cmd_buffer_clear_attachments, which emits the top-of-pass
clears, to use the data provided in anv_cmd_state::attachments. This
prepares for deferring each attachment clear to the first subpass that
uses the attachment.
2016-01-14 22:53:05 -08:00
Chad Versace
a4b045ca44 anv: Add anv_cmd_state::attachments
This array contains attachment state when recording a renderpass instance.
It's populated on each call to anv_cmd_buffer_set_pass.

The data is currently set but unused. We'll use it later to defer each
attachment clear to the subpass that first uses the attachment.
2016-01-14 22:53:05 -08:00
Jason Ekstrand
5d1c2736b6 i965/fs/generator: Change a comment as per jordan's suggestion 2016-01-14 22:03:15 -08:00
Jason Ekstrand
6be517b20e i965/fs: Always set hannel 2 of texture headers in some stages 2016-01-14 20:42:47 -08:00
Jason Ekstrand
e1d13cd058 i965/fs/generator: Take an actual shader stage rather than a string 2016-01-14 20:27:56 -08:00
Jason Ekstrand
47af950df5 anv/apply_pipeline_layout: Stomp texture array size to 1 2016-01-14 18:58:25 -08:00
Jason Ekstrand
6483d3f8fe nir/spirv: Fix texture return types
We were just hard-coding everything to a vec4.  This meant we weren't
handling shadow samplers at all and integer things were getting the wrong
return type.
2016-01-14 18:48:57 -08:00
Kristian Høgsberg Kristensen
2eb52198ff vk: Fix struct field indentation 2016-01-14 15:18:40 -08:00
Chad Versace
5dea9d0039 anv: Document anv_cmd_state::current_pipeline
It's the value of PIPELINE_SELECT.PipelineSelection.
2016-01-14 13:18:40 -08:00
Chad Versace
ed33ccde63 anv: Make vkBeginCommandBuffer reset the command buffer
If its the command buffer's first call to vkBeginCommandBuffer, we must
*initialize* the command buffer's state. Otherwise, we must *reset* its
state. In both cases, let's use anv_ResetCommandBuffer.

From the Vulkan 1.0 spec:

   If a command buffer is in the executable state and the command buffer
   was allocated from a command pool with the
   VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
   vkBeginCommandBuffer implicitly resets the command buffer, behaving
   as if vkResetCommandBuffer had been called with
   VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
   the command buffer in the recording state.
2016-01-14 13:14:40 -08:00
Chad Versace
ea20389320 anv: Add FIXME for vkResetCommandPool
vkResetCommandPool currently destroys its command buffers. The Vulkan
1.0 spec requires that it only reset them:

    Resetting a command pool recycles all of the resources from all of
    the command buffers allocated from the command pool back to the
    command pool. All command buffers that have been allocated from the
    command pool are put in the initial state.
2016-01-14 13:14:40 -08:00
Chad Versace
20fd816b6b anv: Remove duplicate func prototype
anv_private.h declared anv_cmd_buffer_begin_subpass twice.
2016-01-14 13:14:40 -08:00
Chad Versace
0415dfcfe7 anv/meta: Add FINISHME for clearing multi-layer framebuffers 2016-01-14 13:14:40 -08:00
Jason Ekstrand
32f8bcb84f i965/vec4: Use UW type for multiply into accumulator on GEN8+
BDW adds the following restriction: "When multiplying DW x DW, the dst
cannot be accumulator."
2016-01-14 12:04:25 -08:00
Jason Ekstrand
45349acad0 Merge remote-tracking branch 'mesa-public/master' into vulkan
This fixes the bitfieldextract and bitfieldinsert CTS tests
2016-01-14 11:36:27 -08:00
Ilia Mirkin
e94ef885bb st/mesa: use surface format to generate mipmaps when available
This fixes the recently posted mipmap + texture views piglit test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-01-14 14:28:04 -05:00
Marek Olšák
dc96a18d24 radeonsi: don't miss changes to SPI_TMPRING_SIZE
I'm not sure about the consequences of this bug, but it's definitely
dangerous.

This applies to SI, CIK, VI.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-14 19:55:41 +01:00
Charmaine Lee
6303231a1d svga: add DXGenMips command support
For those formats that support hw mipmap generation, use the
DXGenMips command. Otherwise fallback to the mipmap generation utility.

Tested with piglit, OpenGL apps (Heaven, Turbine, Cinebench)

v2: make sure the texture surface was created with the render target bind flag
    set relocation flag to SVGA_RELOC_WRITE for the texture surface

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-14 10:44:25 -07:00
Charmaine Lee
78e628ae43 svga: add num-generate-mipmap HUD query
The actual increment of the num-generate-mipmap counter will be done
in a subsequent patch when hw generate mipmap is supported.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-14 10:39:53 -07:00
Charmaine Lee
3038e8984d gallium/st: add pipe_context::generate_mipmap()
This patch adds a new interface to support hardware mipmap generation.
PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify
if this new interface is supported; if not supported, the state tracker will
fallback to mipmap generation by rendering/texturing.

v2: add PIPE_CAP_GENERATE_MIPMAP to the disabled section for all drivers
v3: add format to the generate_mipmap interface to allow mipmap generation
    using a format other than the resource format
v4: fix return type of trace_context_generate_mipmap()

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-14 10:39:53 -07:00
Brian Paul
b1e11f4d71 st/mesa: declare struct pipe_screen in st_cb_bufferobjects.h
To silence a compiler warning.  Trivial.
2016-01-14 10:38:18 -07:00
Matt Turner
b82e26a6a4 nir: Lower bitfield_extract.
The OpenGL specifications for bitfieldExtract() says:

   The result will be undefined if <offset> or <bits> is negative, or if
   the sum of <offset> and <bits> is greater than the number of bits
   used to store the operand.

Therefore passing bits=32, offset=0 is legal and defined in GLSL.

But the earlier SM5 ubfe/ibfe opcodes are specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits
of the width operand, making them not able to implement the GLSL-specified
behavior directly.

This commit adds ubfe/ibfe operations from SM5 and a lowering pass for
bitfield_extract to to handle the trivial case of <bits> = 32 as

   bitfieldExtract:
      bits > 31 ? value : bfe(value, offset, bits)

Fixes:
   ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
2016-01-14 09:28:01 -08:00
Matt Turner
15640ee77a nir: Handle <bits>=32 case in bitfield_insert lowering.
The OpenGL specifications for bitfieldInsert() says:

   The result will be undefined if <offset> or <bits> is negative, or if
   the sum of <offset> and <bits> is greater than the number of bits
   used to store the operand.

Therefore passing bits=32, offset=0 is legal and defined in GLSL.

But the earlier SM5 bfi opcode is specified to accept a bitfield width
ranging from 0-31. As such, Intel and AMD instructions read only the low
5 bits of the width operand, making them not able to implement the
GLSL-specified behavior directly.

This commit fixes the lowering of bitfield_insert to handle the trivial
case of <bits> = 32 as

   bitfieldInsert:
      bits > 31 ? insert : bfi(bfm(bits, offset), insert, base)

Fixes:
   ES31-CTS.shader_bitfield_operation.bitfieldInsert.uint_2
   ES31-CTS.shader_bitfield_operation.bitfieldInsert.uvec4_3
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
2016-01-14 09:27:52 -08:00
Jason Ekstrand
f46f4e4886 nir/spirv: Add initial support for Vertex/Instance index 2016-01-14 09:12:32 -08:00
Jason Ekstrand
3d0fac7aca vulkan.h: Pull in 1.0.1 header 2016-01-14 08:37:54 -08:00
Jason Ekstrand
24a6fcba77 vulkan-1.0.0: Bump the version to 1.0.0 2016-01-14 08:26:37 -08:00
Jason Ekstrand
c310fb032d vulkan-1.0.0: Rework memory barriers 2016-01-14 08:09:39 -08:00
Brian Paul
6470435190 st/mesa: add check for color logicop in blit_copy_pixels()
We check that a bunch of raster operations are disabled in
blit_copy_pixels().  We also need to check that color logicop is
disabled.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:08:21 -07:00
Jason Ekstrand
b14a78cfb8 vulkan-1.0.0: No-op WSI changes 2016-01-14 08:02:44 -08:00
Jason Ekstrand
6d3322d0e5 vulkan-1.0.0: Make extents unsigned 2016-01-14 08:00:18 -08:00
Jason Ekstrand
b57c72d964 vulkan-1.0.0: Rework blits to use four offsets 2016-01-14 07:59:37 -08:00
Jason Ekstrand
f6cae99294 vulkan-1.0.0: Split out command buffer inheritance info 2016-01-14 07:45:15 -08:00
Jason Ekstrand
f99f847412 vulkan-1.0.0: Re-order some structs in the header 2016-01-14 07:43:05 -08:00
Jason Ekstrand
aab9517f3d vulkan-1.0.0: Misc. field and argument renames 2016-01-14 07:41:45 -08:00
Jason Ekstrand
d877095e66 vulkan-1.0.0: Get rid of MIPMAP_MODE_BASE 2016-01-14 07:32:16 -08:00
Jason Ekstrand
7b81637762 vulkan-1.0.0: Convert pPreserveAttachments to a uint32_t 2016-01-14 07:30:46 -08:00
Jason Ekstrand
802f00219a anv/device: Update features and limits 2016-01-14 07:30:46 -08:00
Jason Ekstrand
08735ba91c anv/cmd_buffer: Fix setting of viewport/scissor count 2016-01-14 07:30:46 -08:00
Jason Ekstrand
ed4fe3e9ba anv/state: Respect SamplerCreateInfo.anisotropyEnable 2016-01-14 07:30:46 -08:00
Jason Ekstrand
8a81d136f8 anv/image: Fill out VkSubresourceLayout.arrayPitch 2016-01-14 07:30:46 -08:00
BogDan Vatra
102c74277f WIP: Partially upgrade to vulkan v0.221.0
TODO, make use of:
- VkPhysicalDeviceFeatures.drawIndirectFirstInstance,
- VkPhysicalDeviceFeatures.inheritedQueries
- VkPhysicalDeviceLimits.timestampComputeAndGraphics
- VkSubmitInfo.pWaitDstStageMask
- VkSubresourceLayout.arrayPitch
- VkSamplerCreateInfo.anisotropyEnable
2016-01-14 07:30:46 -08:00
Nicolai Hähnle
e976860638 gallium/radeon: do not reallocate user memory buffers
The whole point of AMD_pinned_memory is that applications don't have to map
buffers via OpenGL - but they're still allowed to, so make sure we don't break
the link between buffer object and user memory unless explicitly instructed
to.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:41:24 -05:00
Nicolai Hähnle
321140d563 gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFER
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:41:04 -05:00
Nicolai Hähnle
08c71740ad gallium/radeon: reset valid_buffer_range on PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
This accomodates a streaming pattern where the discard flag is set when the
application wraps back to the beginning of the buffer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:40:00 -05:00