Commit graph

88376 commits

Author SHA1 Message Date
Ilia Mirkin
ee3ebe68f9 gallium: add PIPE_CAP_TGSI_FS_FBFETCH
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:09 -05:00
Ilia Mirkin
1393999541 gallium: add FBFETCH opcode to retrieve the current sample value
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:08 -05:00
Ilia Mirkin
376316e963 mesa: allow BlendBarrier to be used without support for full fb fetch
The extension spec is not currently published, so it's a bit premature
to require it for BlendBarrier usage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:08 -05:00
Ilia Mirkin
2dd4cdeb4e glsl: avoid treating fb fetches as output reads to be lowered
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 21:13:08 -05:00
Dave Airlie
75f858cc33 radv/meta: split color renderpass creation out.
This is just prep work for layered clears, it doesn't change
anything.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-17 08:22:48 +10:00
Bas Nieuwenhuizen
5ae4de18d9 radv: Support multiple devices.
Pretty straightforward. Also deleted the big comment block as it
is a pretty standard pattern for filling in arrays.

Also removed the error message on non-existent devices, as getting
7 errors printed to the console each time you enumerate the
devices is pretty confusing.

v2: Add constant for number of DRM devices.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-01-16 22:15:22 +01:00
Bas Nieuwenhuizen
8406f79d6a radv: Get physical device from radv_device instead of the instance.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-01-16 22:15:22 +01:00
Ilia Mirkin
0baa639f76 nvc0: true up exposing of the HW_METRIC_QUERY_GROUP for maxwell
This had been updated in one place but not the other.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-01-16 16:04:55 -05:00
Dave Airlie
d4392a877c radv/ac: use ctx->voidt in more places. (v2)
Just noticed this while in the area.

v2: one replacement was incorrect.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-17 06:55:51 +10:00
Dave Airlie
3634dfd9e7 radv/meta: consolidate the depth stencil clear renderpasses
We only need one per samples (maybe not even that), reduce
all the unneeded ones.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-17 06:51:25 +10:00
Ilia Mirkin
5eeebca12f nv50/ir: handle new DDIV op which will be used for double divisions
The existing lowering is in place to lower that to RCP + MUL, or fancier
things down the line if necessary.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-01-16 14:45:46 -05:00
Nicolai Hähnle
6be4a40430 tgsi: add DDIV instruction
Double-precision division, to allow more precision than a DRCP + DMUL
sequence.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-16 20:17:22 +01:00
Nicolai Hähnle
5e94e5bb9b radeonsi: fix R600_DEBUG=nooptvariant
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2017-01-16 20:16:18 +01:00
Kenneth Graunke
7a2b65a1d7 i965: Make BLORP disable the NP Z PMA stall fix.
This may fix GPU hangs on Gen8.  I don't know if it does though.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-16 10:15:06 -08:00
Kenneth Graunke
d2590eb65f i965: Enable OpenGL 4.5 on Haswell.
Everything is in place and the test results look solid.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-01-16 10:13:23 -08:00
Marek Olšák
d523415609 radeonsi: implement GL_FIXED vertex format
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 18:07:08 +01:00
Marek Olšák
018fb2ecb3 radeonsi: implement 32-bit SNORM/UNORM/SSCALED/USCALED vertex formats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 18:07:08 +01:00
Marek Olšák
44e9b67229 radeonsi: make fix_fetch 64-bit
v2: add u_bit_consecutive64

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 18:07:08 +01:00
Thomas Hindoe Paaboel Andersen
8daf6de3de gallium/hud: avoid buffer overrun
Renaming data sources was added in
e8bb97ce30
It was possible to use a new name longer than
the name array in hud_graph of 128. This
patch truncates the name to fit the array.

CC: Marek Olšák <marek.olsak@amd.com>

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2017-01-16 18:07:08 +01:00
Marek Olšák
0d9a4efce9 gallium/radeon: add GPU-shaders-busy HUD query
It should be close to the GPU load, but it can be much lower if something
is stalling shader execution (e.g. CP DMA).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 15:35:30 +01:00
Marek Olšák
aa0de724c7 gallium/radeon: make the GPU load / GRBM_STATUS monitoring extensible
The next patch will add SPI_BUSY monitoring.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 15:35:30 +01:00
Marek Olšák
935d58ac73 radeonsi: show average results per frame for perf counters in HUD
so that the graphs are independent from FPS.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 15:35:30 +01:00
Marek Olšák
1fe7c8d3c9 gallium/hud: disable queries during HUD draw calls
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 15:35:30 +01:00
Marek Olšák
5b2eddc40f gallium/hud: increase the vertex buffer size for background quads
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-16 15:35:30 +01:00
Nayan Deshmukh
4b0e9babc6 st/va: delay calling begin_frame until we have all parameters
If begin_frame is called before setting intra_matrix and
non_intra_matrix it leads to segmentation faults when
vl_mpeg12_decoder.c is used.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92634
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-01-16 15:09:01 +01:00
Kenneth Graunke
5597b2b243 i965: Use align1 mode for barrier messages.
In commit 7428e6f86a we switched the barrier SEND message's
destination type to UW to avoid problems in SIMD16 compute shaders.

Tessellation control shaders also use barriers, and in vec4 mode, we
were emitting them in align16 mode.  The simulator warns that only UD,
D, F, and DF are valid destination types - UW is technically illegal.

So, switch to align1 mode.  Either mode should work fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-15 16:49:58 -08:00
Ilia Mirkin
dd39e48726 nvc0/ir: emit FMZ flag when requested on FFMA
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-01-15 13:13:58 -05:00
Connor Abbott
c9b74f3f03 nir/gcm: fix a bug with metadata handling
We were using impl->num_blocks, but that isn't guaranteed to be
up-to-date until after the block_index metadata is required. If we were
unlucky, this could lead to overwriting memory.

Noticed by inspection.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-14 18:18:17 -05:00
Lionel Landwerlin
bf8e1f9e7b radv: generate entrypoints from vk.xml
v2: rework entry point iteration (Jason)
    cleanup unused imports

v3: don't drop header installation (Emil)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-14 19:29:44 +00:00
Lionel Landwerlin
c7fc310cd1 anv: generate entry points from vk.xml
v2: rework entry point iteration (Jason)
    cleanup unused imports

v3: don't drop header installation (Emil)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-14 19:29:44 +00:00
Lionel Landwerlin
dbd677efb4 vulkan: add API registry
Signed-off: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-14 19:29:44 +00:00
Lionel Landwerlin
60bc90cea8 include: update Vulkan headers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-14 19:29:44 +00:00
Andres Rodriguez
1e1bddf15a radv: make device extension setup dynamic
Each physical device may have different extensions than one another.
Furthermore, depending on the software stack, some extensions may not be
accessible.

If an extension is conditional, it can be registered only when
necessary.

v2: removed unused function and fixed indentation

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-01-14 14:20:17 +01:00
Andres Rodriguez
5323efb685 radv: rename global extension properties structs
All extension arrays are global, but only one of them refers to instance
extensions.

The device extension array refers to extensions that are common across
all physical devices. This disctinction will be more imporant once we
have dynamic extension support for devices.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-01-14 14:20:12 +01:00
Andres Rodriguez
0eb8b6a3e1 radv: use a winsys context per-queue, instead of per device v2
Queues are independent execution streams. The vulkan spec provides no
ordering guarantees for different queues.

By using a single context for all queues, we are forcing all commands
into an unecessary FIFO ordering.

This change is a preparation step to allow our-of-ordering scheduling of
certain work tasks.

v2: Fix a rebase error with radv_QueueSubmit() and trace_bo
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-01-14 14:19:41 +01:00
Timothy Arceri
772cd31048 nir: optimise min/max fadd combos
shader-db results BDW:

total instructions in shared programs: 13060410 -> 13060313 (-0.00%)
instructions in affected programs: 24533 -> 24436 (-0.40%)
helped: 88
HURT: 0

total cycles in shared programs: 256585692 -> 256586698 (0.00%)
cycles in affected programs: 647290 -> 648296 (0.16%)
helped: 35
HURT: 30

Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-01-14 23:26:22 +11:00
Kenneth Graunke
0d5071db5e i965: Move Gen4-5 interpolation stuff to brw_wm_prog_data.
This fixes glxgears rendering, which had surprisingly been broken since
late October!  Specifically, commit 91d61fbf7c.

glxgears uses glShadeModel(GL_FLAT) when drawing the main portion of the
gears, then uses glShadeModel(GL_SMOOTH) for drawing the Gouraud-shaded
inner portion of the gears.  This results in the same fragment program
having two different state-dependent interpolation maps: one where
gl_Color is flat, and another where it's smooth.

The problem is that there's only one gen4_fragment_program, so it can't
store both.  Each FS compile would trash the last one.  But, the FS
compiles are cached, so the first one would store FLAT, and the second
would see a matching program in the cache and never bother to compile
one with SMOOTH.  (Clearing the program cache on every draw made it
render correctly.)

Instead, move it to brw_wm_prog_data, where we can keep a copy for
every specialization of the program.  The only downside is bloating
the structure a bit, but we can tighten that up a bit if we need to.
This also lets us kill gen4_fragment_program entirely!

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2017-01-13 17:25:48 -08:00
Grazvydas Ignotas
40a8f9e6f2 anv: remove some unused macros and functions
VK_ICD_WSI_PLATFORM_MAX is used, but a duplicate from wsi_common.h .

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-13 16:52:27 -08:00
Jason Ekstrand
3b80481965 anv: Default PointSize to 1.0 if not written by the shader
The Vulkan rules for point size are a bit whacky.  If you only have a
vertex shader and you use points, then you must write PointSize in your
vertex shader.  If you have a geometry or tessellation shader, then it's
dependent on the shaderTessellationAndGeometryPointSize device feature.
From the Vulkan 1.0.38 specification:

   "shaderTessellationAndGeometryPointSize indicates whether the
   PointSize built-in decoration is available in the tessellation
   control, tessellation evaluation, and geometry shader stages. If this
   feature is not enabled, members decorated with the PointSize built-in
   decoration must not be read from or written to and all points written
   from a tessellation or geometry shader will have a size of 1.0. This
   also indicates whether shader modules can declare the
   TessellationPointSize capability for tessellation control and
   evaluation shaders, or if the shader modules can declare the
   GeometryPointSize capability for geometry shaders. An implementation
   supporting this feature must also support one or both of the
   tessellationShader or geometryShader features."

In other words, if the feature is disbled (the client can disable
features!) then they don't write PointSize and we provide a 1.0 default
but if the feature is enabled, they do write PointSize and we use the
one they wrote in the shader.  There are at least two valid ways we can
implement this:

 1) Track whether or not shaderTessellationAndGeometryPointSize is
    enabled and set the 3DSTATE_SF bits based on that and what stages
    are enabled, ignoring the shader source.

 2) Just look at the last geometry stage VUE map and see if they wrote
    PointSize and set the 3DSTATE_SF accordingly.

The second solution is the easiest and the most robust against invalid
usage of the Vulkan API, so we choose to go with that one.

This fixes all of the dEQP-VK.tessellation.primitive_discard.*point_mode
tests.  The tests are also broken because they unconditionally enable
shaderTessellationAndGeometryPointSize if it's supported by the
implementation and then don't write PointSize in the evaluation shader.
However, since this is the "robust against invalid API usage" solution,
the tests happily pass. :-)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-01-13 16:31:17 -08:00
Jason Ekstrand
99d497c5b6 anv/pipeline: Replace get_fs_input_map with get_last_vue_prog_data
This lets us delete a helper from genX_pipeline.c

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-01-13 16:31:17 -08:00
Juan A. Suarez Romero
56ee2df4bf i965/vec4: Fix mapping attributes
This patch reverts 57bab6708f, which was
causing issues with ILK and earlier VS programs.

1. brw_nir.c: Revert "i965/vec4/nir: vec4 also needs to remap vs attributes"

   Do not perform a remap in vec4 backend. Rather, do it later when
   setup attributes

2. brw_vec4.cpp: This fixes mapping ATTRx to proper GRFn.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99391
[jordan.l.justen@intel.com: merge Juan's two patches from bugzilla]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-01-13 16:23:32 -08:00
Kenneth Graunke
fed4afc5bb anv: Move nir_lower_wpos_center after dead variable elimination.
When multiple shader stages exist in the same SPIR-V module, we compile
all entry points and their inputs/outputs, then dead code eliminate the
ones not related to the specific entry point later.

nir_lower_wpos_center was being run prior to eliminating those random
other variables, which made it trip up, thinking it found gl_FragCoord
when it actually found something else like gl_PerVertex[3].

Fixes dEQP-VK.spirv_assembly.instruction.graphics.module.same_module.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-13 15:00:38 -08:00
Kenneth Graunke
99c019e1d4 i965: Fix textureGather with RG32I/UI on Gen7.
According to the "Gather4 R32G32_FLOAT Bug" internal documentation
page, the R32G32_UINT and R32G32_SINT formats are affected by the
same bug as R32G32_FLOAT.  Applying the same workarounds should be
viable - apparently the R32G32_FLOAT_LD format shouldn't corrupt
integer data which is NaN or other sketchy floating point values.

One irritating caveat is that, because it's a FLOAT format, the
alpha channel or any set to SCS_ONE return 0x3f8 (1.0) rather than
integer 1.  So we need shader code to whack those channels to 1.

Fixes GL45-CTS.texture_gather.plain-gather-int-cube-rg on Haswell.

v2: Fix swizzle component zeroing (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-13 11:57:06 -08:00
Bas Nieuwenhuizen
6d2fb04f09 radv: Support loader interface version 3.
Port of 1e41d7f7b0:
"anv: Support loader interface version 3 (patch v2)"

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-13 19:11:17 +01:00
Boyan Ding
ddd27ef462 mesa/get: Remove unused extra_ARB_viewport_array
Unused since 0a7691ee (mesa: Enable enums for OES_viewport_array).
Silence a warning of unused variable.

Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-13 17:09:22 +00:00
Boyan Ding
dc18ec8b24 xlib: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: handle the final case in glXCreateContextAttribsARB]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-13 16:24:40 +00:00
Boyan Ding
2d05425d3e radeon: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: handle the all cases]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-13 16:24:32 +00:00
Boyan Ding
056cfa558c nouveau: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
2017-01-13 16:24:32 +00:00
Boyan Ding
0ee4c4a732 glX_proto_send.py: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
2017-01-13 16:24:32 +00:00
Boyan Ding
1411fbd50d loader/dri3: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
2017-01-13 16:24:32 +00:00