diff --git a/.pick_status.json b/.pick_status.json
index 7343bea4b19..9b6f075d8cb 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -130,7 +130,7 @@
         "description": "pan/mdg: Fix calculation of available work registers",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "c6ed8bf77cb8b78f98ff4924816ee052a9aa2c7b"
     },
diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index 4ff34238f06..1d93cc44f16 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -394,7 +394,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
         /* The number of vec4 work registers available depends on the number of
          * register-mapped uniforms and the shader stage. By ABI we limit blend
          * shaders to 8 registers, should be lower XXX */
-        unsigned rmu = ctx->info->push.count / 4;
+        int rmu = ctx->info->push.count / 4;
         int work_count = ctx->inputs->is_blend ? 8 : 16 - MAX2(rmu - 8, 0);
 
        /* No register allocation to do with no SSA */