From 4c0b3b5d9e39e2d3ba58bd54835645e68e4bce77 Mon Sep 17 00:00:00 2001 From: Icecream95 Date: Thu, 29 Apr 2021 11:27:28 +1200 Subject: [PATCH] pan/mdg: Fix calculation of available work registers Make the rmu variable signed; otherwise the MAX2 has no effect and work_count can end up being larger than 16. Fixes INSTR_OPERAND_FAULTs in SuperTuxKart. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4707 Fixes: c6ed8bf77cb ("panfrost: Fix uniform_count on Midgard") Reviewed-by: Boris Brezillon Part-of: (cherry picked from commit f85b7aa5d409ffcc7e0ae013f43068a698d3517e) --- .pick_status.json | 2 +- src/panfrost/midgard/midgard_ra.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 7343bea4b19..9b6f075d8cb 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -130,7 +130,7 @@ "description": "pan/mdg: Fix calculation of available work registers", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "c6ed8bf77cb8b78f98ff4924816ee052a9aa2c7b" }, diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index 4ff34238f06..1d93cc44f16 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -394,7 +394,7 @@ allocate_registers(compiler_context *ctx, bool *spilled) /* The number of vec4 work registers available depends on the number of * register-mapped uniforms and the shader stage. By ABI we limit blend * shaders to 8 registers, should be lower XXX */ - unsigned rmu = ctx->info->push.count / 4; + int rmu = ctx->info->push.count / 4; int work_count = ctx->inputs->is_blend ? 8 : 16 - MAX2(rmu - 8, 0); /* No register allocation to do with no SSA */