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mesa/src/mesa/drivers/dri/i965/brw_eu_emit.c

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Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
s/Tungsten Graphics/VMware/ Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/alanh@tungstengraphics.com/alanh@vmware.com/ s/jens@tungstengraphics.com/jowen@vmware.com/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g s/keithw\?@tungstengraphics.com/keithw@vmware.com/g s/michel@tungstengraphics.com/daenzer@vmware.com/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/zack@tungstengraphics.com/zackr@vmware.com/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <brianp@vmware.com>
2014-01-17 16:27:50 +00:00
Intel funded Tungsten Graphics to
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
develop this 3D driver.
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
**********************************************************************/
/*
* Authors:
s/Tungsten Graphics/VMware/ Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/alanh@tungstengraphics.com/alanh@vmware.com/ s/jens@tungstengraphics.com/jowen@vmware.com/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g s/keithw\?@tungstengraphics.com/keithw@vmware.com/g s/michel@tungstengraphics.com/daenzer@vmware.com/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/zack@tungstengraphics.com/zackr@vmware.com/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <brianp@vmware.com>
2014-01-17 16:27:50 +00:00
* Keith Whitwell <keithw@vmware.com>
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
*/
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_eu.h"
util: Move ralloc to a new src/util directory. For a long time, we've wanted a place to put utility code which isn't directly tied to Mesa or Gallium internals. This patch creates a new src/util directory for exactly that purpose, and builds the contents as libmesautil.la. ralloc seemed like a good first candidate. These days, it's directly used by mesa/main, i965, i915, and r300g, so keeping it in src/glsl didn't make much sense. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> v2 (Jason Ekstrand): More realloc uses and some scons fixes Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-02-24 23:39:14 -08:00
#include "util/ralloc.h"
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/***********************************************************************
* Internal helper for constructing instructions
*/
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
static void guess_execution_size(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn,
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
struct brw_reg reg)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
if (reg.width == BRW_WIDTH_8 && p->compressed) {
brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_16);
} else {
/* Register width definitions are compatible with BRW_EXECUTE_* enums. */
brw_inst_set_exec_size(brw, insn, reg.width);
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
/**
* Prior to Sandybridge, the SEND instruction accepted non-MRF source
* registers, implicitly moving the operand to a message register.
*
* On Sandybridge, this is no longer the case. This function performs the
* explicit move; it should be called before emitting a SEND instruction.
*/
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
2011-08-22 10:35:24 -07:00
void
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
gen6_resolve_implied_move(struct brw_compile *p,
struct brw_reg *src,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_reg_nr)
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
if (brw->gen < 6)
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
return;
i965: Make gen6_resolve_implied_move a no-op for MRF sources. Attempting to move an MRF to a MRF is not only pointless, it will fail because MRFs are read-only, resulting in garbage in your register. If we already set up a MRF source, there's nothing to resolve anyway. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-11-14 19:49:54 -08:00
if (src->file == BRW_MESSAGE_REGISTER_FILE)
return;
i965: Fix null register use in Sandybridge implied move resolution. Fixes regressions caused by commit 9a21bc6401, namely GPU hangs when running gnome-shell or compiz (Mesa bugs #35820 and #35853). I incorrectly refactored the case that dealt with ARF_NULL; even in that case, the source register needs to be changed to the MRF. NOTE: This is a candidate for the 7.10 branch (if 9a21bc6401 is cherry-picked, take this one too).
2011-04-03 00:57:30 -07:00
if (src->file != BRW_ARCHITECTURE_REGISTER_FILE || src->nr != BRW_ARF_NULL) {
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 16:57:02 -07:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965: Fix null register use in Sandybridge implied move resolution. Fixes regressions caused by commit 9a21bc6401, namely GPU hangs when running gnome-shell or compiz (Mesa bugs #35820 and #35853). I incorrectly refactored the case that dealt with ARF_NULL; even in that case, the source register needs to be changed to the MRF. NOTE: This is a candidate for the 7.10 branch (if 9a21bc6401 is cherry-picked, take this one too).
2011-04-03 00:57:30 -07:00
brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
retype(*src, BRW_REGISTER_TYPE_UD));
brw_pop_insn_state(p);
}
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
*src = brw_message_reg(msg_reg_nr);
}
i965: Mad hacks to avoid using MRFs on Ivybridge. Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-09 00:32:46 -07:00
static void
gen7_convert_mrf_to_grf(struct brw_compile *p, struct brw_reg *reg)
{
i965: Cite the Ivybridge PRM for why the fake MRF range is what it is. The exact text is in the public docs, so we should cite those. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-07-10 13:16:13 -07:00
/* From the Ivybridge PRM, Volume 4 Part 3, page 218 ("send"):
i965: Bump Ivybridge's fake MRF range to g112-127 instead of g111-126. When I originally implemented the hack to use GRFs 111+ as fake MRFs, I did so purely to avoid rewriting all the code that dealt with MRFs. However, it turns out that a similar hack is actually required. Newly discovered language in the BSpec indicates that SEND instructions with EOT set "should" use g112-g127 as their source registers. Based on assertions in the simulator, this is actually a requirement on certain platforms. Since we're faking MRFs already, we may as well use the officially sanctioned range. My guess is that we avoided this issue because we seldom use m0: URB writes in the new VS backend start at m1, and RT writes in the new FS backend start at m2. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-01-17 08:08:25 -08:00
* "The send with EOT should use register space R112-R127 for <src>. This is
* to enable loading of a new thread into the same slot while the message
* with EOT for current thread is pending dispatch."
*
* Since we're pretending to have 16 MRFs anyway, we may as well use the
* registers required for messages with EOT.
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965/eu: Change gen == 7 to gen >= 7 in a couple brw_eu_emit.c cases. Broadwell is going to use the brw_eu_emit.c code soon. We want to get the fake MRF handling and URB HWord channel mask handling. We don't need the CMP thread switch workaround, though. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 07:26:30 -07:00
if (brw->gen >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
i965: Mad hacks to avoid using MRFs on Ivybridge. Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-09 00:32:46 -07:00
reg->file = BRW_GENERAL_REGISTER_FILE;
i965/fs: Fix rendering corruption in unigine tropics. We were allocating registers into the MRF hack region, resulting in sparkly renering in a few of the scenes. We could do better allocation by making an MRF class, having MRFs conflict with the corresponding GRFs, and tracking the live intervals of the "MRF"s and setting up the conflicts. But this is way easier for the moment. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-01-27 12:54:11 -08:00
reg->nr += GEN7_MRF_HACK_START;
i965: Mad hacks to avoid using MRFs on Ivybridge. Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-09 00:32:46 -07:00
}
}
i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values. On released hardware, values 4-6 are overloaded. For normal registers, they mean UB/B/DF. But for immediates, they mean UV/VF/V. Previously, we just created #defines for each name, reusing the same value. This meant we could directly splat the brw_reg::type field into the assembly encoding, which was fairly nice, and worked well. Unfortunately, Broadwell makes this infeasible: the HF and DF types are represented as different numeric values depending on whether the source register is an immediate or not. To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to an abstract enum that has a unique value for each register type, and write translation functions. One nice benefit is that we can add assertions about register files and generations. I've chosen not to convert brw_reg::type to the enum, since converting it caused a lot of trouble due to C++ enum rules (even though it's defined in an extern "C" block...). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 00:33:56 -08:00
/**
* Convert a brw_reg_type enumeration value into the hardware representation.
*
* The hardware encoding may depend on whether the value is an immediate.
*/
unsigned
brw_reg_type_to_hw_type(const struct brw_context *brw,
enum brw_reg_type type, unsigned file)
{
if (file == BRW_IMMEDIATE_VALUE) {
const static int imm_hw_types[] = {
[BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,
[BRW_REGISTER_TYPE_D] = BRW_HW_REG_TYPE_D,
[BRW_REGISTER_TYPE_UW] = BRW_HW_REG_TYPE_UW,
[BRW_REGISTER_TYPE_W] = BRW_HW_REG_TYPE_W,
[BRW_REGISTER_TYPE_F] = BRW_HW_REG_TYPE_F,
[BRW_REGISTER_TYPE_UB] = -1,
[BRW_REGISTER_TYPE_B] = -1,
[BRW_REGISTER_TYPE_UV] = BRW_HW_REG_IMM_TYPE_UV,
[BRW_REGISTER_TYPE_VF] = BRW_HW_REG_IMM_TYPE_VF,
[BRW_REGISTER_TYPE_V] = BRW_HW_REG_IMM_TYPE_V,
i965: Add support for Broadwell's new register types. Broadwell introduces support for Q, UQ, and HF types. It also extends DF support to allow immediate values. Irritatingly, although HF and DF both support immediates, they're represented by a different value depending on the register file. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 01:53:26 -08:00
[BRW_REGISTER_TYPE_DF] = GEN8_HW_REG_IMM_TYPE_DF,
[BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_IMM_TYPE_HF,
[BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
[BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values. On released hardware, values 4-6 are overloaded. For normal registers, they mean UB/B/DF. But for immediates, they mean UV/VF/V. Previously, we just created #defines for each name, reusing the same value. This meant we could directly splat the brw_reg::type field into the assembly encoding, which was fairly nice, and worked well. Unfortunately, Broadwell makes this infeasible: the HF and DF types are represented as different numeric values depending on whether the source register is an immediate or not. To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to an abstract enum that has a unique value for each register type, and write translation functions. One nice benefit is that we can add assertions about register files and generations. I've chosen not to convert brw_reg::type to the enum, since converting it caused a lot of trouble due to C++ enum rules (even though it's defined in an extern "C" block...). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 00:33:56 -08:00
};
assert(type < ARRAY_SIZE(imm_hw_types));
assert(imm_hw_types[type] != -1);
i965: Add support for Broadwell's new register types. Broadwell introduces support for Q, UQ, and HF types. It also extends DF support to allow immediate values. Irritatingly, although HF and DF both support immediates, they're represented by a different value depending on the register file. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 01:53:26 -08:00
assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_DF);
i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values. On released hardware, values 4-6 are overloaded. For normal registers, they mean UB/B/DF. But for immediates, they mean UV/VF/V. Previously, we just created #defines for each name, reusing the same value. This meant we could directly splat the brw_reg::type field into the assembly encoding, which was fairly nice, and worked well. Unfortunately, Broadwell makes this infeasible: the HF and DF types are represented as different numeric values depending on whether the source register is an immediate or not. To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to an abstract enum that has a unique value for each register type, and write translation functions. One nice benefit is that we can add assertions about register files and generations. I've chosen not to convert brw_reg::type to the enum, since converting it caused a lot of trouble due to C++ enum rules (even though it's defined in an extern "C" block...). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 00:33:56 -08:00
return imm_hw_types[type];
} else {
/* Non-immediate registers */
const static int hw_types[] = {
[BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,
[BRW_REGISTER_TYPE_D] = BRW_HW_REG_TYPE_D,
[BRW_REGISTER_TYPE_UW] = BRW_HW_REG_TYPE_UW,
[BRW_REGISTER_TYPE_W] = BRW_HW_REG_TYPE_W,
[BRW_REGISTER_TYPE_UB] = BRW_HW_REG_NON_IMM_TYPE_UB,
[BRW_REGISTER_TYPE_B] = BRW_HW_REG_NON_IMM_TYPE_B,
[BRW_REGISTER_TYPE_F] = BRW_HW_REG_TYPE_F,
[BRW_REGISTER_TYPE_UV] = -1,
[BRW_REGISTER_TYPE_VF] = -1,
[BRW_REGISTER_TYPE_V] = -1,
i965: Add BRW_REGISTER_TYPE_DF. Ivybridge, Baytrail, and Haswell support double float register types, but do not support them as immediate values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 01:49:18 -08:00
[BRW_REGISTER_TYPE_DF] = GEN7_HW_REG_NON_IMM_TYPE_DF,
i965: Add support for Broadwell's new register types. Broadwell introduces support for Q, UQ, and HF types. It also extends DF support to allow immediate values. Irritatingly, although HF and DF both support immediates, they're represented by a different value depending on the register file. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 01:53:26 -08:00
[BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_NON_IMM_TYPE_HF,
[BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
[BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values. On released hardware, values 4-6 are overloaded. For normal registers, they mean UB/B/DF. But for immediates, they mean UV/VF/V. Previously, we just created #defines for each name, reusing the same value. This meant we could directly splat the brw_reg::type field into the assembly encoding, which was fairly nice, and worked well. Unfortunately, Broadwell makes this infeasible: the HF and DF types are represented as different numeric values depending on whether the source register is an immediate or not. To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to an abstract enum that has a unique value for each register type, and write translation functions. One nice benefit is that we can add assertions about register files and generations. I've chosen not to convert brw_reg::type to the enum, since converting it caused a lot of trouble due to C++ enum rules (even though it's defined in an extern "C" block...). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 00:33:56 -08:00
};
assert(type < ARRAY_SIZE(hw_types));
assert(hw_types[type] != -1);
i965: Add BRW_REGISTER_TYPE_DF. Ivybridge, Baytrail, and Haswell support double float register types, but do not support them as immediate values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 01:49:18 -08:00
assert(brw->gen >= 7 || type < BRW_REGISTER_TYPE_DF);
i965: Add support for Broadwell's new register types. Broadwell introduces support for Q, UQ, and HF types. It also extends DF support to allow immediate values. Irritatingly, although HF and DF both support immediates, they're represented by a different value depending on the register file. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 01:53:26 -08:00
assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_HF);
i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values. On released hardware, values 4-6 are overloaded. For normal registers, they mean UB/B/DF. But for immediates, they mean UV/VF/V. Previously, we just created #defines for each name, reusing the same value. This meant we could directly splat the brw_reg::type field into the assembly encoding, which was fairly nice, and worked well. Unfortunately, Broadwell makes this infeasible: the HF and DF types are represented as different numeric values depending on whether the source register is an immediate or not. To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to an abstract enum that has a unique value for each register type, and write translation functions. One nice benefit is that we can add assertions about register files and generations. I've chosen not to convert brw_reg::type to the enum, since converting it caused a lot of trouble due to C++ enum rules (even though it's defined in an extern "C" block...). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-12-10 00:33:56 -08:00
return hw_types[type];
}
}
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
i965: Make some EU emit code for DP read/write messages non-static. We keep building these strange interfaces for DP read/write where there's a helper function with some partially-specific, partially-general controls, which is used in exactly one place in code generation. Making these public will let us set up those instructions in the one place they're to be generated.
2011-08-07 13:16:06 -07:00
void
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_set_dest(struct brw_compile *p, brw_inst *inst, struct brw_reg dest)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Use Compr4 instruction compression mode on G4X and newer. No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
2009-11-06 17:45:13 -08:00
if (dest.file != BRW_ARCHITECTURE_REGISTER_FILE &&
dest.file != BRW_MESSAGE_REGISTER_FILE)
i965: add some register number assertions Haven't seen failures yet, but if/when there are, more investigation will be done.
2009-03-13 09:17:08 -06:00
assert(dest.nr < 128);
i965: Mad hacks to avoid using MRFs on Ivybridge. Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-09 00:32:46 -07:00
gen7_convert_mrf_to_grf(p, &dest);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_reg_file(brw, inst, dest.file);
brw_inst_set_dst_reg_type(brw, inst, brw_reg_type_to_hw_type(brw, dest.type,
dest.file));
brw_inst_set_dst_address_mode(brw, inst, dest.address_mode);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
if (dest.address_mode == BRW_ADDRESS_DIRECT) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_da_reg_nr(brw, inst, dest.nr);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
brw_inst_set_dst_da1_subreg_nr(brw, inst, dest.subnr);
Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1 Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <keithp@keithp.com>
2008-11-01 14:38:19 -07:00
if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
dest.hstride = BRW_HORIZONTAL_STRIDE_1;
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_hstride(brw, inst, dest.hstride);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_da16_subreg_nr(brw, inst, dest.subnr / 16);
brw_inst_set_da16_writemask(brw, inst, dest.dw1.bits.writemask);
i965: Fix writemask != 0 assertions on Sandybridge. This fixes myriads of regressions since commit 169f9c030c16d1247a3a7629 ("i965: Add an assertion that writemask != NULL for non-ARFs."). On Sandybridge, our control flow handling (such as brw_IF) does: brw_set_dest(p, insn, brw_imm_w(0)); insn->bits1.branch_gen6.jump_count = 0; This results in a IMM destination with zero for the writemask. IMM destinations are rather bizarre, but the code has been working for ages, so I'm loathe to change it. Fixes glxgears on Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-17 11:54:05 -07:00
if (dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_MESSAGE_REGISTER_FILE) {
assert(dest.dw1.bits.writemask != 0);
}
i965: Quote the PRM on a HorzStride subtlety Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 11:40:29 -08:00
/* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
* Although Dst.HorzStride is a don't care for Align16, HW needs
* this to be programmed as "01".
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_hstride(brw, inst, 1);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_ia_subreg_nr(brw, inst, dest.subnr);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* These are different sizes in align1 vs align16:
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
brw_inst_set_dst_ia1_addr_imm(brw, inst,
dest.dw1.bits.indirect_offset);
Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1 Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <keithp@keithp.com>
2008-11-01 14:38:19 -07:00
if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
dest.hstride = BRW_HORIZONTAL_STRIDE_1;
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_hstride(brw, inst, dest.hstride);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_ia16_addr_imm(brw, inst,
dest.dw1.bits.indirect_offset);
i965: Set the destination horiz stride even for da16, as SNB seems to need it.
2010-08-20 15:01:11 -07:00
/* even ignored in da16, still need to set as '01' */
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dst_hstride(brw, inst, 1);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
}
/* NEW: Set the execution size based on dest.width and
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
* inst->compression_control:
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
guess_execution_size(p, inst, dest);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Add assertion for another requirement about types. This catches a failure in the FS backend.
2010-09-04 21:04:58 -07:00
extern int reg_type_size[];
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
static void
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
validate_reg(const struct brw_context *brw, brw_inst *inst, struct brw_reg reg)
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
{
int hstride_for_reg[] = {0, 1, 2, 4};
int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
int width_for_reg[] = {1, 2, 4, 8, 16};
int execsize_for_reg[] = {1, 2, 4, 8, 16};
int width, hstride, vstride, execsize;
i965: Add assertion for another requirement about types. This catches a failure in the FS backend.
2010-09-04 21:04:58 -07:00
if (reg.file == BRW_IMMEDIATE_VALUE) {
/* 3.3.6: Region Parameters. Restriction: Immediate vectors
* mean the destination has to be 128-bit aligned and the
* destination horiz stride has to be a word.
*/
if (reg.type == BRW_REGISTER_TYPE_V) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(hstride_for_reg[brw_inst_dst_hstride(brw, inst)] *
reg_type_size[brw_inst_dst_reg_type(brw, inst)] == 2);
i965: Add assertion for another requirement about types. This catches a failure in the FS backend.
2010-09-04 21:04:58 -07:00
}
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
return;
i965: Add assertion for another requirement about types. This catches a failure in the FS backend.
2010-09-04 21:04:58 -07:00
}
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
Revert "i965: Check reg.nr for BRW_ARF_NULL instead of reg.file." This reverts commit ecdda414d361ab4430fd5747c9217687c1f3d63f. Commit was supposed to be a simple typo fix. Clearly needs more investigating. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63688
2013-04-18 21:51:49 -07:00
reg.file == BRW_ARF_NULL)
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
return;
assert(reg.hstride >= 0 && reg.hstride < Elements(hstride_for_reg));
hstride = hstride_for_reg[reg.hstride];
if (reg.vstride == 0xf) {
vstride = -1;
} else {
assert(reg.vstride >= 0 && reg.vstride < Elements(vstride_for_reg));
vstride = vstride_for_reg[reg.vstride];
}
assert(reg.width >= 0 && reg.width < Elements(width_for_reg));
width = width_for_reg[reg.width];
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_exec_size(brw, inst) >= 0 &&
brw_inst_exec_size(brw, inst) < Elements(execsize_for_reg));
execsize = execsize_for_reg[brw_inst_exec_size(brw, inst)];
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
/* Restrictions from 3.3.10: Register Region Restrictions. */
/* 3. */
assert(execsize >= width);
/* 4. */
if (execsize == width && hstride != 0) {
assert(vstride == -1 || vstride == width * hstride);
}
/* 5. */
if (execsize == width && hstride == 0) {
/* no restriction on vstride. */
}
/* 6. */
if (width == 1) {
assert(hstride == 0);
}
/* 7. */
if (execsize == 1 && width == 1) {
assert(hstride == 0);
assert(vstride == 0);
}
/* 8. */
if (vstride == 0 && hstride == 0) {
assert(width == 1);
}
/* 10. Check destination issues. */
}
i965: Switch types D->UD when possible to allow compaction. Number of compacted instructions: 827404 -> 833045 (0.68%) Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 15:54:05 -07:00
static bool
is_compactable_immediate(unsigned imm)
{
/* We get the low 12 bits as-is. */
imm &= ~0xfff;
/* We get one bit replicated through the top 20 bits. */
return imm == 0 || imm == 0xfffff000;
}
i965: Make some EU emit code for DP read/write messages non-static. We keep building these strange interfaces for DP read/write where there's a helper function with some partially-specific, partially-general controls, which is used in exactly one place in code generation. Making these public will let us set up those instructions in the one place they're to be generated.
2011-08-07 13:16:06 -07:00
void
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_set_src0(struct brw_compile *p, brw_inst *inst, struct brw_reg reg)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965/gen7: Add some safety checks for send messages from GRFs.
2012-11-09 11:38:14 -08:00
struct brw_context *brw = p->brw;
i965: Fix two broken asserts in brw_eu_emit These were looking in the wrong field. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-07-06 20:11:05 +12:00
if (reg.file != BRW_ARCHITECTURE_REGISTER_FILE)
i965: add some register number assertions Haven't seen failures yet, but if/when there are, more investigation will be done.
2009-03-13 09:17:08 -06:00
assert(reg.nr < 128);
i965: Mad hacks to avoid using MRFs on Ivybridge. Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-09 00:32:46 -07:00
gen7_convert_mrf_to_grf(p, &reg);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw->gen >= 6 && (brw_inst_opcode(brw, inst) == BRW_OPCODE_SEND ||
brw_inst_opcode(brw, inst) == BRW_OPCODE_SENDC)) {
i965/gen7: Add some safety checks for send messages from GRFs.
2012-11-09 11:38:14 -08:00
/* Any source modifiers or regions will be ignored, since this just
* identifies the MRF/GRF to start reading the message contents from.
* Check for some likely failures.
*/
assert(!reg.negate);
assert(!reg.abs);
assert(reg.address_mode == BRW_ADDRESS_DIRECT);
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
validate_reg(brw, inst, reg);
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_reg_file(brw, inst, reg.file);
brw_inst_set_src0_reg_type(brw, inst,
brw_reg_type_to_hw_type(brw, reg.type, reg.file));
brw_inst_set_src0_abs(brw, inst, reg.abs);
brw_inst_set_src0_negate(brw, inst, reg.negate);
brw_inst_set_src0_address_mode(brw, inst, reg.address_mode);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
if (reg.file == BRW_IMMEDIATE_VALUE) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_imm_ud(brw, inst, reg.dw1.ud);
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
i965: Emit ARF:UD for non-present src1 on Gen6+. Enables the next commits to compact more instructions. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-02 14:14:11 -07:00
/* The Bspec's section titled "Non-present Operands" claims that if src0
* is an immediate that src1's type must be the same as that of src0.
*
* The SNB+ DataTypeIndex instruction compaction tables contain mappings
* that do not follow this rule. E.g., from the IVB/HSW table:
*
* DataTypeIndex 18-Bit Mapping Mapped Meaning
* 3 001000001011111101 r:f | i:vf | a:ud | <1> | dir |
*
* And from the SNB table:
*
* DataTypeIndex 18-Bit Mapping Mapped Meaning
* 8 001000000111101100 a:w | i:w | a:ud | <1> | dir |
*
* Neither of these cause warnings from the simulator when used,
* compacted or otherwise. In fact, all compaction mappings that have an
* immediate in src0 use a:ud for src1.
*
* The GM45 instruction compaction tables do not contain mapped meanings
* so it's not clear whether it has the restriction. We'll assume it was
* lifted on SNB. (FINISHME: decode the GM45 tables and check.)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_reg_file(brw, inst, BRW_ARCHITECTURE_REGISTER_FILE);
i965: Emit ARF:UD for non-present src1 on Gen6+. Enables the next commits to compact more instructions. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-02 14:14:11 -07:00
if (brw->gen < 6) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_reg_type(brw, inst,
brw_inst_src0_reg_type(brw, inst));
i965: Emit ARF:UD for non-present src1 on Gen6+. Enables the next commits to compact more instructions. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-02 14:14:11 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_reg_type(brw, inst, BRW_HW_REG_TYPE_UD);
i965: Emit ARF:UD for non-present src1 on Gen6+. Enables the next commits to compact more instructions. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-02 14:14:11 -07:00
}
i965: Emit 0.0:F sources with type VF instead. Number of compacted instructions: 817752 -> 827404 (1.18%) Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-02 14:47:55 -07:00
/* Compacted instructions only have 12-bits (plus 1 for the other 20)
* for immediate values. Presumably the hardware engineers realized
* that the only useful floating-point value that could be represented
* in this format is 0.0, which can also be represented as a VF-typed
* immediate, so they gave us the previously mentioned mapping on IVB+.
*
* Strangely, we do have a mapping for imm:f in src1, so we don't need
* to do this there.
*
* If we see a 0.0:F, change the type to VF so that it can be compacted.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_imm_ud(brw, inst) == 0x0 &&
brw_inst_src0_reg_type(brw, inst) == BRW_HW_REG_TYPE_F) {
brw_inst_set_src0_reg_type(brw, inst, BRW_HW_REG_IMM_TYPE_VF);
i965: Emit 0.0:F sources with type VF instead. Number of compacted instructions: 817752 -> 827404 (1.18%) Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-02 14:47:55 -07:00
}
i965: Switch types D->UD when possible to allow compaction. Number of compacted instructions: 827404 -> 833045 (0.68%) Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 15:54:05 -07:00
/* There are no mappings for dst:d | i:d, so if the immediate is suitable
* set the types to :UD so the instruction can be compacted.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (is_compactable_immediate(brw_inst_imm_ud(brw, inst)) &&
brw_inst_cond_modifier(brw, inst) == BRW_CONDITIONAL_NONE &&
brw_inst_src0_reg_type(brw, inst) == BRW_HW_REG_TYPE_D &&
brw_inst_dst_reg_type(brw, inst) == BRW_HW_REG_TYPE_D) {
brw_inst_set_src0_reg_type(brw, inst, BRW_HW_REG_TYPE_UD);
brw_inst_set_dst_reg_type(brw, inst, BRW_HW_REG_TYPE_UD);
i965: Switch types D->UD when possible to allow compaction. Number of compacted instructions: 827404 -> 833045 (0.68%) Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 15:54:05 -07:00
}
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
if (reg.address_mode == BRW_ADDRESS_DIRECT) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_da_reg_nr(brw, inst, reg.nr);
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
brw_inst_set_src0_da1_subreg_nr(brw, inst, reg.subnr);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_da16_subreg_nr(brw, inst, reg.subnr / 16);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_ia_subreg_nr(brw, inst, reg.subnr);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
brw_inst_set_src0_ia1_addr_imm(brw, inst, reg.dw1.bits.indirect_offset);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_ia_subreg_nr(brw, inst, reg.dw1.bits.indirect_offset);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
if (reg.width == BRW_WIDTH_1 &&
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_exec_size(brw, inst) == BRW_EXECUTE_1) {
brw_inst_set_src0_hstride(brw, inst, BRW_HORIZONTAL_STRIDE_0);
brw_inst_set_src0_width(brw, inst, BRW_WIDTH_1);
brw_inst_set_src0_vstride(brw, inst, BRW_VERTICAL_STRIDE_0);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_hstride(brw, inst, reg.hstride);
brw_inst_set_src0_width(brw, inst, reg.width);
brw_inst_set_src0_vstride(brw, inst, reg.vstride);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_da16_swiz_x(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X));
brw_inst_set_src0_da16_swiz_y(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y));
brw_inst_set_src0_da16_swiz_z(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z));
brw_inst_set_src0_da16_swiz_w(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W));
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* This is an oddity of the fact we're using the same
* descriptions for registers in align_16 as align_1:
*/
if (reg.vstride == BRW_VERTICAL_STRIDE_8)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_vstride(brw, inst, BRW_VERTICAL_STRIDE_4);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
else
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src0_vstride(brw, inst, reg.vstride);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
}
}
i965: Reformat brw_set_src1 so it can be easily found with grep.
2014-05-02 14:49:24 -07:00
void
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_set_src1(struct brw_compile *p, brw_inst *inst, struct brw_reg reg)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
fix a couple of cases where a message reg is used as an instruction source.
2006-09-01 14:18:06 +00:00
assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
i965: Fix two broken asserts in brw_eu_emit These were looking in the wrong field. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-07-06 20:11:05 +12:00
if (reg.file != BRW_ARCHITECTURE_REGISTER_FILE)
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 14:10:52 -08:00
assert(reg.nr < 128);
i965: add some register number assertions Haven't seen failures yet, but if/when there are, more investigation will be done.
2009-03-13 09:17:08 -06:00
i965: Mad hacks to avoid using MRFs on Ivybridge. Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-09 00:32:46 -07:00
gen7_convert_mrf_to_grf(p, &reg);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
validate_reg(brw, inst, reg);
i965: Add a bit of validation for some ISA restrictions in the docs.
2010-09-03 21:37:00 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_reg_file(brw, inst, reg.file);
brw_inst_set_src1_reg_type(brw, inst,
brw_reg_type_to_hw_type(brw, reg.type, reg.file));
brw_inst_set_src1_abs(brw, inst, reg.abs);
brw_inst_set_src1_negate(brw, inst, reg.negate);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* Only src1 can be immediate in two-argument instructions.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_src0_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
if (reg.file == BRW_IMMEDIATE_VALUE) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_imm_ud(brw, inst, reg.dw1.ud);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* This is a hardware restriction, which may or may not be lifted
* in the future:
*/
assert (reg.address_mode == BRW_ADDRESS_DIRECT);
intel: Silence compiler warnings.
2009-12-28 18:46:15 -08:00
/* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_da_reg_nr(brw, inst, reg.nr);
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
brw_inst_set_src1_da1_subreg_nr(brw, inst, reg.subnr);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_da16_subreg_nr(brw, inst, reg.subnr / 16);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
if (reg.width == BRW_WIDTH_1 &&
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_exec_size(brw, inst) == BRW_EXECUTE_1) {
brw_inst_set_src1_hstride(brw, inst, BRW_HORIZONTAL_STRIDE_0);
brw_inst_set_src1_width(brw, inst, BRW_WIDTH_1);
brw_inst_set_src1_vstride(brw, inst, BRW_VERTICAL_STRIDE_0);
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_hstride(brw, inst, reg.hstride);
brw_inst_set_src1_width(brw, inst, reg.width);
brw_inst_set_src1_vstride(brw, inst, reg.vstride);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Fix else and brace placement in brw_eu_emit.c. I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-04 16:55:59 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_da16_swiz_x(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X));
brw_inst_set_src1_da16_swiz_y(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y));
brw_inst_set_src1_da16_swiz_z(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z));
brw_inst_set_src1_da16_swiz_w(brw, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W));
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* This is an oddity of the fact we're using the same
* descriptions for registers in align_16 as align_1:
*/
if (reg.vstride == BRW_VERTICAL_STRIDE_8)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_vstride(brw, inst, BRW_VERTICAL_STRIDE_4);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
else
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_src1_vstride(brw, inst, reg.vstride);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
}
}
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
/**
* Set the Message Descriptor and Extended Message Descriptor fields
* for SEND messages.
*
* \note This zeroes out the Function Control bits, so it must be called
* \b before filling out any message-specific data. Callers can
* choose not to fill in irrelevant bits; they will be zero.
*/
static void
brw_set_message_descriptor(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *inst,
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
enum brw_message_target sfid,
unsigned msg_length,
unsigned response_length,
bool header_present,
bool end_of_thread)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
brw_set_src1(p, inst, brw_imm_d(0));
i965: Adjust set_message_descriptor to handle non-sends We're about to be using this infrastructure to build descriptors in src1 of non-send instructions, when preparing to do an indirect send. Don't accidentally clobber the conditionalmod field of those instructions with SFID bits, which aren't part of the descriptor. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-03 12:02:25 +12:00
/* For indirect sends, `inst` will not be the SEND/SENDC instruction
* itself; instead, it will be a MOV/OR into the address register.
*
* In this case, we avoid setting the extended message descriptor bits,
* since they go on the later SEND/SENDC instead and if set here would
* instead clobber the conditionalmod bits.
*/
unsigned opcode = brw_inst_opcode(brw, inst);
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
brw_inst_set_sfid(brw, inst, sfid);
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_mlen(brw, inst, msg_length);
brw_inst_set_rlen(brw, inst, response_length);
brw_inst_set_eot(brw, inst, end_of_thread);
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 5) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_header_present(brw, inst, header_present);
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
}
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
static void brw_set_math_message( struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *inst,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned function,
unsigned integer_type,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
bool low_precision,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned dataType )
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
struct brw_context *brw = p->brw;
i965: Fix message and response length calculations for INT DIV. Both POW and INT DIV need a message length of 2; previously, we only checked for POW. Also, BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER has a response length of 2; previously, we only checked for SINCOS. We don't use this message, but in case we ever decide to, we may as well fix it now. While we're at it, just move these computations into brw_set_math_message, since they're entirely based on the function. This fixes it for both brw_math and the old backend's brw_math_16. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-28 17:37:52 -07:00
unsigned msg_length;
unsigned response_length;
/* Infer message length from the function */
switch (function) {
case BRW_MATH_FUNCTION_POW:
case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT:
case BRW_MATH_FUNCTION_INT_DIV_REMAINDER:
case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
msg_length = 2;
break;
default:
msg_length = 1;
break;
}
/* Infer response length from the function */
switch (function) {
case BRW_MATH_FUNCTION_SINCOS:
case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
response_length = 2;
break;
default:
response_length = 1;
break;
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Drop the confusing saturate argument to math instruction setup. This was ridiculous. We were ignoring the inst->header.saturate flag in the case of math and only math. On gen4, we would leave inst->header.saturate in place if it happened to be set, which would end up being applied to the implicit mov and thus trash the first argument. On gen6, we would overwrite inst->header.saturate with the saturate flag from the argument, which was not set appropriately in brw_vec4_emit.cpp, and was only not a bug due to our incompetence at coalescing saturate moves. By ripping the argument out and making saturate work just like all the other brw_eu_emit.c code generation, we can avoid both these classes of bugs. Fixes piglit fog-modes, and the new specific fs-saturate-exp2 case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628 NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-06 14:59:39 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_set_message_descriptor(p, inst, BRW_SFID_MATH,
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
msg_length, response_length, false, false);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_math_msg_function(brw, inst, function);
brw_inst_set_math_msg_signed_int(brw, inst, integer_type);
brw_inst_set_math_msg_precision(brw, inst, low_precision);
brw_inst_set_math_msg_saturate(brw, inst, brw_inst_saturate(brw, inst));
brw_inst_set_math_msg_data_type(brw, inst, dataType);
brw_inst_set_saturate(brw, inst, 0);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
static void brw_set_ff_sync_message(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
bool allocate,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned response_length,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
bool end_of_thread)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
brw_set_message_descriptor(p, insn, BRW_SFID_URB,
1, response_length, true, end_of_thread);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_urb_opcode(brw, insn, 1); /* FF_SYNC */
brw_inst_set_urb_allocate(brw, insn, allocate);
/* The following fields are not used by FF_SYNC: */
brw_inst_set_urb_global_offset(brw, insn, 0);
brw_inst_set_urb_swizzle_control(brw, insn, 0);
brw_inst_set_urb_used(brw, insn, 0);
brw_inst_set_urb_complete(brw, insn, 0);
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
static void brw_set_urb_message( struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn,
i965: Allow C++ type safety in the use of enum brw_urb_write_flags. (From a suggestion by Francisco Jerez) If an enum represents a bitfield of flags, e.g.: enum E { A = 1, B = 2, C = 4, D = 8, }; then C++ normally prohibits statements like this: enum E x = A | B; because A and B are implicitly converted to ints before OR-ing them, and an int can't be stored in an enum without a type cast. C, on the other hand, allows an int to be implicitly converted to an enum without casting. In the past we've dealt with this situation by storing flag bitfields as ints. This avoids ugly casting at the expense of some type safety that C++ would normally have offered (e.g. we get no warning if we accidentally use the wrong enum type). However, we can get the best of both worlds if we override the | operator. The ugly casting is confined to the operator overload, and we still get the benefit of C++ making sure we don't use the wrong enum type. v2: Remove unnecessary comment and unnecessary use of "enum" keyword. Use static_cast. Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2013-08-23 13:19:19 -07:00
enum brw_urb_write_flags flags,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_length,
unsigned response_length,
unsigned offset,
unsigned swizzle_control )
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
{
i965: Fix inconsistent indentation in brw_eu_emit.c. Most of these functions used three spaces for the first level of indentation, but four spaces for the next level. One used tabs and then three spaces. Some used 3/4 in a then block but 3/3 in the else block. Normally I try to avoid field days like this, but since the functions were so inconsistent, even internally, it was making it difficult to edit without introducing spurious whitespace changes. So, just get it over with. git diff -b shows 0 lines changed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-07 11:59:06 -07:00
struct brw_context *brw = p->brw;
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw->gen < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
assert(brw->gen < 7 || !(flags & BRW_URB_WRITE_ALLOCATE));
assert(brw->gen >= 7 || !(flags & BRW_URB_WRITE_PER_SLOT_OFFSET));
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
brw_set_message_descriptor(p, insn, BRW_SFID_URB,
i965: Combine 4 boolean args of brw_urb_WRITE into a flags bitfield. The arguments to brw_urb_WRITE() were getting pretty unwieldy, and we have to add more flags to support geometry shaders anyhow. Also plumb these flags through brw_clip_emit_vue(), brw_set_urb_message(), and the vec4_instruction class. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-08-10 21:13:33 -07:00
msg_length, response_length, true,
flags & BRW_URB_WRITE_EOT);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (flags & BRW_URB_WRITE_OWORD) {
assert(msg_length == 2); /* header + one OWORD of data */
brw_inst_set_urb_opcode(brw, insn, BRW_URB_OPCODE_WRITE_OWORD);
} else {
brw_inst_set_urb_opcode(brw, insn, BRW_URB_OPCODE_WRITE_HWORD);
}
brw_inst_set_urb_global_offset(brw, insn, offset);
brw_inst_set_urb_swizzle_control(brw, insn, swizzle_control);
if (brw->gen < 8) {
brw_inst_set_urb_complete(brw, insn, !!(flags & BRW_URB_WRITE_COMPLETE));
}
if (brw->gen < 7) {
brw_inst_set_urb_allocate(brw, insn, !!(flags & BRW_URB_WRITE_ALLOCATE));
brw_inst_set_urb_used(brw, insn, !(flags & BRW_URB_WRITE_UNUSED));
i965: Fix inconsistent indentation in brw_eu_emit.c. Most of these functions used three spaces for the first level of indentation, but four spaces for the next level. One used tabs and then three spaces. Some used 3/4 in a then block but 3/3 in the else block. Normally I try to avoid field days like this, but since the functions were so inconsistent, even internally, it was making it difficult to edit without introducing spurious whitespace changes. So, just get it over with. git diff -b shows 0 lines changed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-07 11:59:06 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_urb_per_slot_offset(brw, insn,
!!(flags & BRW_URB_WRITE_PER_SLOT_OFFSET));
i965: Fix inconsistent indentation in brw_eu_emit.c. Most of these functions used three spaces for the first level of indentation, but four spaces for the next level. One used tabs and then three spaces. Some used 3/4 in a then block but 3/3 in the else block. Normally I try to avoid field days like this, but since the functions were so inconsistent, even internally, it was making it difficult to edit without introducing spurious whitespace changes. So, just get it over with. git diff -b shows 0 lines changed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-07 11:59:06 -07:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Make some EU emit code for DP read/write messages non-static. We keep building these strange interfaces for DP read/write where there's a helper function with some partially-specific, partially-general controls, which is used in exactly one place in code generation. Making these public will let us set up those instructions in the one place they're to be generated.
2011-08-07 13:16:06 -07:00
void
brw_set_dp_write_message(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned binding_table_index,
unsigned msg_control,
unsigned msg_type,
unsigned msg_length,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
bool header_present,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned last_render_target,
unsigned response_length,
unsigned end_of_thread,
unsigned send_commit_msg)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
struct brw_context *brw = p->brw;
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
unsigned sfid;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 7) {
i965: Use Ivybridge's "Legacy Data Port" for reads/writes. Using the constant cache for reads isn't going to work for scratch reads (variably-indexed arrays or register spills), as these aren't constant at all. Also, in the new VS backend, use the proper message number for OWord Dual Block Write messages. It's now 10, instead of 9. +205 piglits. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:53 -07:00
/* Use the Render Cache for RT writes; otherwise use the Data Cache */
if (msg_type == GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE)
i965: Rename BRW_MESSAGE_TARGET_* to BRW_SFID_* and document them. When reading the data port code, it was not clear to me what these values meant, nor where I could find them in the documentation. Especially since the latest BSpec and older PRMs document them in radically different places...neither of which are near the descriptions of individual messages. Cite the documentation, and rename them to SFID to signify that these are Shared Function IDs that one can read about in the GPU overview, rather than arbitrary bitfields. While we're add it, make them an enum. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 20:55:35 -07:00
sfid = GEN6_SFID_DATAPORT_RENDER_CACHE;
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
else
sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
/* Use the render cache for all write messages. */
sfid = GEN6_SFID_DATAPORT_RENDER_CACHE;
} else {
sfid = BRW_SFID_DATAPORT_WRITE;
}
i965: Use Ivybridge's "Legacy Data Port" for reads/writes. Using the constant cache for reads isn't going to work for scratch reads (variably-indexed arrays or register spills), as these aren't constant at all. Also, in the new VS backend, use the proper message number for OWord Dual Block Write messages. It's now 10, instead of 9. +205 piglits. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:53 -07:00
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
brw_set_message_descriptor(p, insn, sfid, msg_length, response_length,
header_present, end_of_thread);
i965: Use Ivybridge's "Legacy Data Port" for reads/writes. Using the constant cache for reads isn't going to work for scratch reads (variably-indexed arrays or register spills), as these aren't constant at all. Also, in the new VS backend, use the proper message number for OWord Dual Block Write messages. It's now 10, instead of 9. +205 piglits. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:53 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_binding_table_index(brw, insn, binding_table_index);
brw_inst_set_dp_write_msg_type(brw, insn, msg_type);
brw_inst_set_dp_write_msg_control(brw, insn, msg_control);
brw_inst_set_rt_last(brw, insn, last_render_target);
if (brw->gen < 7) {
brw_inst_set_dp_write_commit(brw, insn, send_commit_msg);
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Make some EU emit code for DP read/write messages non-static. We keep building these strange interfaces for DP read/write where there's a helper function with some partially-specific, partially-general controls, which is used in exactly one place in code generation. Making these public will let us set up those instructions in the one place they're to be generated.
2011-08-07 13:16:06 -07:00
void
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_dp_read_message(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned binding_table_index,
unsigned msg_control,
unsigned msg_type,
unsigned target_cache,
unsigned msg_length,
i965: Add a header_present flag for setting up dp read messages. As of gen7, we can skip the header on some messages, and this can make optimization on those messages much nicer when you've got GRFs instead of MRFs as the source.
2012-11-09 11:17:48 -08:00
bool header_present,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned response_length)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
struct brw_context *brw = p->brw;
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
unsigned sfid;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 7) {
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
if (target_cache == BRW_DATAPORT_READ_TARGET_RENDER_CACHE)
sfid = GEN6_SFID_DATAPORT_RENDER_CACHE;
else
sfid = GEN6_SFID_DATAPORT_SAMPLER_CACHE;
} else {
sfid = BRW_SFID_DATAPORT_READ;
}
brw_set_message_descriptor(p, insn, sfid, msg_length, response_length,
i965: Add a header_present flag for setting up dp read messages. As of gen7, we can skip the header on some messages, and this can make optimization on those messages much nicer when you've got GRFs instead of MRFs as the source.
2012-11-09 11:17:48 -08:00
header_present, false);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_binding_table_index(brw, insn, binding_table_index);
brw_inst_set_dp_read_msg_type(brw, insn, msg_type);
brw_inst_set_dp_read_msg_control(brw, insn, msg_control);
if (brw->gen < 6)
brw_inst_set_dp_read_target_cache(brw, insn, target_cache);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Expose brw_set_sampler_message for use outside brw_eu_emit.c. brw_SAMPLE is full of complex workarounds for original Broadwater hardware, and I'd rather avoid all that for my next Ivybridge patch. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-01-26 05:33:19 -08:00
void
brw_set_sampler_message(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *inst,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned binding_table_index,
unsigned sampler,
unsigned msg_type,
unsigned response_length,
unsigned msg_length,
unsigned header_present,
unsigned simd_mode,
unsigned return_format)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
struct brw_context *brw = p->brw;
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_set_message_descriptor(p, inst, BRW_SFID_SAMPLER, msg_length,
i965: Factor out code for setting Message Descriptors. Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 21:09:08 -07:00
response_length, header_present, false);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_binding_table_index(brw, inst, binding_table_index);
brw_inst_set_sampler(brw, inst, sampler);
brw_inst_set_sampler_msg_type(brw, inst, msg_type);
if (brw->gen >= 5) {
brw_inst_set_sampler_simd_mode(brw, inst, simd_mode);
} else if (brw->gen == 4 && !brw->is_g4x) {
brw_inst_set_sampler_return_format(brw, inst, return_format);
i965: new integrated graphics chipset support
2008-01-29 11:13:53 +08:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Add low-level support for indirect sends This provides a reasonable place to enforce the hardware restriction that indirect descriptors must be in a0.0 Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-03 11:44:25 +12:00
void brw_set_indirect_send_descriptor(struct brw_compile *p,
brw_inst *insn,
unsigned sfid,
struct brw_reg descriptor)
{
/* Only a0.0 may be used as SEND's descriptor operand. */
assert(descriptor.file == BRW_ARCHITECTURE_REGISTER_FILE);
assert(descriptor.type == BRW_REGISTER_TYPE_UD);
assert(descriptor.nr == BRW_ARF_ADDRESS);
assert(descriptor.subnr == 0);
brw_set_message_descriptor(p, insn, sfid, 0, 0, false, false);
brw_set_src1(p, insn, descriptor);
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
static void
gen7_set_dp_scratch_message(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *inst,
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
bool write,
bool dword,
bool invalidate_after_read,
unsigned num_regs,
unsigned addr_offset,
unsigned mlen,
unsigned rlen,
bool header_present)
{
const struct brw_context *brw = p->brw;
assert(num_regs == 1 || num_regs == 2 || num_regs == 4 ||
(brw->gen >= 8 && num_regs == 8));
brw_set_message_descriptor(p, inst, GEN7_SFID_DATAPORT_DATA_CACHE,
mlen, rlen, header_present, false);
brw_inst_set_dp_category(brw, inst, 1); /* Scratch Block Read/Write msgs */
brw_inst_set_scratch_read_write(brw, inst, write);
brw_inst_set_scratch_type(brw, inst, dword);
brw_inst_set_scratch_invalidate_after_read(brw, inst, invalidate_after_read);
brw_inst_set_scratch_block_size(brw, inst, ffs(num_regs) - 1);
brw_inst_set_scratch_addr_offset(brw, inst, addr_offset);
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Make some EU emit code for DP read/write messages non-static. We keep building these strange interfaces for DP read/write where there's a helper function with some partially-specific, partially-general controls, which is used in exactly one place in code generation. Making these public will let us set up those instructions in the one place they're to be generated.
2011-08-07 13:16:06 -07:00
#define next_insn brw_next_insn
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
brw_next_insn(struct brw_compile *p, unsigned opcode)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: increase the brw eu instruction store size dynamically Here is the final patch to enable dynamic eu instruction store size: increase the brw eu instruction store size dynamically instead of just allocating it statically with a constant limit. This would fix something that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would limit it to 10000'. v2: comments from ken, do not hardcode the eu limit to (1024 * 1024) Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:38:44 +08:00
if (p->nr_insn + 1 > p->store_size) {
p->store_size <<= 1;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
p->store = reralloc(p->mem_ctx, p->store, brw_inst, p->store_size);
i965: increase the brw eu instruction store size dynamically Here is the final patch to enable dynamic eu instruction store size: increase the brw eu instruction store size dynamically instead of just allocating it statically with a constant limit. This would fix something that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would limit it to 10000'. v2: comments from ken, do not hardcode the eu limit to (1024 * 1024) Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:38:44 +08:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Move program dump to a helper function in brw_eu.c. It's going to get more complicated when we do instruction compaction. This also introduces putting the program offset in the output. v2: Use next_insn_offset in brw_get_program(), too. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 11:50:42 +01:00
p->next_insn_offset += 16;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
insn = &p->store[p->nr_insn++];
memcpy(insn, p->current, sizeof(*insn));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_opcode(brw, insn, opcode);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
return insn;
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
static brw_inst *
brw_alu1(struct brw_compile *p, unsigned opcode,
struct brw_reg dest, struct brw_reg src)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, opcode);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
return insn;
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
static brw_inst *
brw_alu2(struct brw_compile *p, unsigned opcode,
struct brw_reg dest, struct brw_reg src0, struct brw_reg src1)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, opcode);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
return insn;
}
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
static int
get_3src_subreg_nr(struct brw_reg reg)
{
if (reg.vstride == BRW_VERTICAL_STRIDE_0) {
assert(brw_is_single_value_swizzle(reg.dw1.bits.swizzle));
return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0);
} else {
return reg.subnr / 4;
}
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
static brw_inst *
brw_alu3(struct brw_compile *p, unsigned opcode, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1, struct brw_reg src2)
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *inst = next_insn(p, opcode);
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
gen7_convert_mrf_to_grf(p, &dest);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_access_mode(brw, inst) == BRW_ALIGN_16);
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_MESSAGE_REGISTER_FILE);
assert(dest.nr < 128);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
i965/gen7: Set src/dst types for 3-src instructions. Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
2013-04-17 12:23:54 -07:00
assert(dest.type == BRW_REGISTER_TYPE_F ||
dest.type == BRW_REGISTER_TYPE_D ||
dest.type == BRW_REGISTER_TYPE_UD);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw->gen == 6) {
brw_inst_set_3src_dst_reg_file(brw, inst,
dest.file == BRW_MESSAGE_REGISTER_FILE);
}
brw_inst_set_3src_dst_reg_nr(brw, inst, dest.nr);
brw_inst_set_3src_dst_subreg_nr(brw, inst, dest.subnr / 16);
brw_inst_set_3src_dst_writemask(brw, inst, dest.dw1.bits.writemask);
guess_execution_size(p, inst, dest);
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
assert(src0.file == BRW_GENERAL_REGISTER_FILE);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.nr < 128);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_3src_src0_swizzle(brw, inst, src0.dw1.bits.swizzle);
brw_inst_set_3src_src0_subreg_nr(brw, inst, get_3src_subreg_nr(src0));
brw_inst_set_3src_src0_reg_nr(brw, inst, src0.nr);
brw_inst_set_3src_src0_abs(brw, inst, src0.abs);
brw_inst_set_3src_src0_negate(brw, inst, src0.negate);
brw_inst_set_3src_src0_rep_ctrl(brw, inst,
src0.vstride == BRW_VERTICAL_STRIDE_0);
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
assert(src1.file == BRW_GENERAL_REGISTER_FILE);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.nr < 128);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_3src_src1_swizzle(brw, inst, src1.dw1.bits.swizzle);
brw_inst_set_3src_src1_subreg_nr(brw, inst, get_3src_subreg_nr(src1));
brw_inst_set_3src_src1_reg_nr(brw, inst, src1.nr);
brw_inst_set_3src_src1_abs(brw, inst, src1.abs);
brw_inst_set_3src_src1_negate(brw, inst, src1.negate);
brw_inst_set_3src_src1_rep_ctrl(brw, inst,
src1.vstride == BRW_VERTICAL_STRIDE_0);
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
assert(src2.file == BRW_GENERAL_REGISTER_FILE);
assert(src2.address_mode == BRW_ADDRESS_DIRECT);
assert(src2.nr < 128);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_3src_src2_swizzle(brw, inst, src2.dw1.bits.swizzle);
brw_inst_set_3src_src2_subreg_nr(brw, inst, get_3src_subreg_nr(src2));
brw_inst_set_3src_src2_reg_nr(brw, inst, src2.nr);
brw_inst_set_3src_src2_abs(brw, inst, src2.abs);
brw_inst_set_3src_src2_negate(brw, inst, src2.negate);
brw_inst_set_3src_src2_rep_ctrl(brw, inst,
src2.vstride == BRW_VERTICAL_STRIDE_0);
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 7) {
i965: Remove broken source type assertions from brw_alu3(). Commit 526ffdfc033ab01cf133cb7e8290c65d12ccc9be attempted to generalize the source register type assertions to allow D and UD. However, the src1 and src2 assertions actually checked src0.type against D and UD due to a copy and paste bug. It also began setting the source and destination register types based on dest.type, ignoring src0/src1/src2.type completely. BFE and BFI2 may actually pass mixed D/UD types and expect them to be ignored, which is arguably a bit sloppy, but not too crazy either. This patch simply removes the source register assertions as those values aren't used anyway. It also clarifies the comment above the block that sets the register types. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-06-13 14:55:19 -07:00
/* Set both the source and destination types based on dest.type,
* ignoring the source register types. The MAD and LRP emitters ensure
* that all four types are float. The BFE and BFI2 emitters, however,
* may send us mixed D and UD types and want us to ignore that and use
* the destination type.
i965/gen7: Set src/dst types for 3-src instructions. Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
2013-04-17 12:23:54 -07:00
*/
switch (dest.type) {
case BRW_REGISTER_TYPE_F:
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_3src_src_type(brw, inst, BRW_3SRC_TYPE_F);
brw_inst_set_3src_dst_type(brw, inst, BRW_3SRC_TYPE_F);
i965/gen7: Set src/dst types for 3-src instructions. Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
2013-04-17 12:23:54 -07:00
break;
case BRW_REGISTER_TYPE_D:
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_3src_src_type(brw, inst, BRW_3SRC_TYPE_D);
brw_inst_set_3src_dst_type(brw, inst, BRW_3SRC_TYPE_D);
i965/gen7: Set src/dst types for 3-src instructions. Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
2013-04-17 12:23:54 -07:00
break;
case BRW_REGISTER_TYPE_UD:
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_3src_src_type(brw, inst, BRW_3SRC_TYPE_UD);
brw_inst_set_3src_dst_type(brw, inst, BRW_3SRC_TYPE_UD);
i965/gen7: Set src/dst types for 3-src instructions. Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
2013-04-17 12:23:54 -07:00
break;
}
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
return inst;
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/***********************************************************************
* Convenience routines.
*/
#define ALU1(OP) \
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *brw_##OP(struct brw_compile *p, \
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
struct brw_reg dest, \
struct brw_reg src0) \
{ \
return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \
}
#define ALU2(OP) \
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *brw_##OP(struct brw_compile *p, \
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
struct brw_reg dest, \
struct brw_reg src0, \
struct brw_reg src1) \
{ \
return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \
}
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
#define ALU3(OP) \
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *brw_##OP(struct brw_compile *p, \
i965: Add support for the MAD opcode on gen6+. v2: Fix MRF handling on gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2010-03-22 10:05:42 -07:00
struct brw_reg dest, \
struct brw_reg src0, \
struct brw_reg src1, \
struct brw_reg src2) \
{ \
return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
}
i965: Add back strict type assertions for MAD and LRP. Commit 526ffdfc033ab01cf133cb7e8290c65d12ccc9be relaxed the type assertions in brw_alu3 to allow D/UD types (required by BFE and BFI2). This lost us the strict type checking for MAD and LRP, which require all four types to be float. This patch adds a new ALU3F wrapper which checks these once again. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-06-13 14:55:18 -07:00
#define ALU3F(OP) \
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *brw_##OP(struct brw_compile *p, \
i965: Add back strict type assertions for MAD and LRP. Commit 526ffdfc033ab01cf133cb7e8290c65d12ccc9be relaxed the type assertions in brw_alu3 to allow D/UD types (required by BFE and BFI2). This lost us the strict type checking for MAD and LRP, which require all four types to be float. This patch adds a new ALU3F wrapper which checks these once again. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-06-13 14:55:18 -07:00
struct brw_reg dest, \
struct brw_reg src0, \
struct brw_reg src1, \
struct brw_reg src2) \
{ \
assert(dest.type == BRW_REGISTER_TYPE_F); \
assert(src0.type == BRW_REGISTER_TYPE_F); \
assert(src1.type == BRW_REGISTER_TYPE_F); \
assert(src2.type == BRW_REGISTER_TYPE_F); \
return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
}
i965: Correctly emit the RNDZ instruction. Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14 11:40:19 -07:00
/* Rounding operations (other than RNDD) require two instructions - the first
* stores a rounded value (possibly the wrong way) in the dest register, but
* also sets a per-channel "increment bit" in the flag register. A predicated
* add of 1.0 fixes dest to contain the desired result.
i965: Fix RNDZ and RNDE on Sandybridge and Ivybridge. On gen4/5, the RNDZ and RNDE instructions return floor(x), but set special "round increment bits" in the flag register; a predicated ADD (+1) fixes the result. The documentation still lists '.r' as existing, and says that the predicated add is necessary, but it apparently lies. According to the simulator, BRW_CONDITIONAL_R (7) is not a valid conditional modifier and the RNDZ and RNDE instructions simply produce the correct value. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-11 02:18:24 -07:00
*
* Sandybridge and later appear to round correctly without an ADD.
i965: Correctly emit the RNDZ instruction. Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14 11:40:19 -07:00
*/
#define ROUND(OP) \
void brw_##OP(struct brw_compile *p, \
struct brw_reg dest, \
struct brw_reg src) \
{ \
i965: Use brw->gen in some generation checks. Will simplify the automated conversion if we want to allow compiling the driver for a single generation. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-10 17:44:56 -07:00
struct brw_context *brw = p->brw; \
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *rnd, *add; \
i965: Correctly emit the RNDZ instruction. Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14 11:40:19 -07:00
rnd = next_insn(p, BRW_OPCODE_##OP); \
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, rnd, dest); \
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, rnd, src); \
i965: Correctly emit the RNDZ instruction. Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14 11:40:19 -07:00
\
i965: Use brw->gen in some generation checks. Will simplify the automated conversion if we want to allow compiling the driver for a single generation. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-10 17:44:56 -07:00
if (brw->gen < 6) { \
i965: Fix RNDZ and RNDE on Sandybridge and Ivybridge. On gen4/5, the RNDZ and RNDE instructions return floor(x), but set special "round increment bits" in the flag register; a predicated ADD (+1) fixes the result. The documentation still lists '.r' as existing, and says that the predicated add is necessary, but it apparently lies. According to the simulator, BRW_CONDITIONAL_R (7) is not a valid conditional modifier and the RNDZ and RNDE instructions simply produce the correct value. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-11 02:18:24 -07:00
/* turn on round-increments */ \
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_cond_modifier(brw, rnd, BRW_CONDITIONAL_R); \
i965: Fix RNDZ and RNDE on Sandybridge and Ivybridge. On gen4/5, the RNDZ and RNDE instructions return floor(x), but set special "round increment bits" in the flag register; a predicated ADD (+1) fixes the result. The documentation still lists '.r' as existing, and says that the predicated add is necessary, but it apparently lies. According to the simulator, BRW_CONDITIONAL_R (7) is not a valid conditional modifier and the RNDZ and RNDE instructions simply produce the correct value. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-11 02:18:24 -07:00
add = brw_ADD(p, dest, dest, brw_imm_f(1.0f)); \
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_pred_control(brw, add, BRW_PREDICATE_NORMAL); \
i965: Fix RNDZ and RNDE on Sandybridge and Ivybridge. On gen4/5, the RNDZ and RNDE instructions return floor(x), but set special "round increment bits" in the flag register; a predicated ADD (+1) fixes the result. The documentation still lists '.r' as existing, and says that the predicated add is necessary, but it apparently lies. According to the simulator, BRW_CONDITIONAL_R (7) is not a valid conditional modifier and the RNDZ and RNDE instructions simply produce the correct value. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-11 02:18:24 -07:00
} \
i965: Correctly emit the RNDZ instruction. Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14 11:40:19 -07:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
ALU1(MOV)
ALU2(SEL)
ALU1(NOT)
ALU2(AND)
ALU2(OR)
ALU2(XOR)
ALU2(SHR)
ALU2(SHL)
ALU2(ASR)
ALU1(FRC)
ALU1(RNDD)
ALU2(MAC)
ALU2(MACH)
ALU1(LZD)
ALU2(DP4)
ALU2(DPH)
ALU2(DP3)
ALU2(DP2)
ALU2(LINE)
i965: Use the PLN instruction when possible in interpolation. Saves an instruction in PINTERP, LINTERP, and PIXEL_W from brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have to be laid out differently.
2010-03-10 14:46:27 -08:00
ALU2(PLN)
i965: Add back strict type assertions for MAD and LRP. Commit 526ffdfc033ab01cf133cb7e8290c65d12ccc9be relaxed the type assertions in brw_alu3 to allow D/UD types (required by BFE and BFI2). This lost us the strict type checking for MAD and LRP, which require all four types to be float. This patch adds a new ALU3F wrapper which checks these once again. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-06-13 14:55:18 -07:00
ALU3F(MAD)
ALU3F(LRP)
i965: Add support for emitting and disassembling bit instructions. Specifically bfe - for bitfieldExtract() bfi1 and bfi2 - for bitfieldInsert() bfrev - for bitfieldReverse() cbit - for bitCount() fbh - for findMSB() fbl - for findLSB() Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-04-09 17:56:19 -07:00
ALU1(BFREV)
ALU3(BFE)
ALU2(BFI1)
ALU3(BFI2)
ALU1(FBH)
ALU1(FBL)
ALU1(CBIT)
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 13:01:08 -07:00
ALU2(ADDC)
ALU2(SUBB)
i965: Correctly emit the RNDZ instruction. Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14 11:40:19 -07:00
ROUND(RNDZ)
i965: Add support for ir_unop_round_even via the RNDE instruction.
2010-10-14 14:31:54 -07:00
ROUND(RNDE)
i965: Correctly emit the RNDZ instruction. Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14 11:40:19 -07:00
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
brw_ADD(struct brw_compile *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
i965: Add some validation on BRW_OPCODE_MUL and ADD's arguments. Now that we're playing with other types in brw_fs.cpp, it's easy to trip over issues like these.
2010-09-04 21:28:04 -07:00
{
/* 6.2.2: add */
if (src0.type == BRW_REGISTER_TYPE_F ||
(src0.file == BRW_IMMEDIATE_VALUE &&
src0.type == BRW_REGISTER_TYPE_VF)) {
assert(src1.type != BRW_REGISTER_TYPE_UD);
assert(src1.type != BRW_REGISTER_TYPE_D);
}
if (src1.type == BRW_REGISTER_TYPE_F ||
(src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_VF)) {
assert(src0.type != BRW_REGISTER_TYPE_UD);
assert(src0.type != BRW_REGISTER_TYPE_D);
}
return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
brw_AVG(struct brw_compile *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
i965: Add support for AVG instruction. From the Ivy Bridge PRM, Vol4 Part3 p152: "The avg instruction performs component-wise integer average of src0 and src1 and stores the results in dst. An integer average uses integer upward rounding. It is equivalent to increment one to the addition of src0 and src1 and then apply an arithmetic right shift to this intermediate value." Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2012-07-07 08:28:46 -07:00
{
assert(dest.type == src0.type);
assert(src0.type == src1.type);
switch (src0.type) {
case BRW_REGISTER_TYPE_B:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
break;
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 14:54:01 -07:00
unreachable("Bad type for brw_AVG");
i965: Add support for AVG instruction. From the Ivy Bridge PRM, Vol4 Part3 p152: "The avg instruction performs component-wise integer average of src0 and src1 and stores the results in dst. An integer average uses integer upward rounding. It is equivalent to increment one to the addition of src0 and src1 and then apply an arithmetic right shift to this intermediate value." Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2012-07-07 08:28:46 -07:00
}
return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1);
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
brw_MUL(struct brw_compile *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
i965: Add some validation on BRW_OPCODE_MUL and ADD's arguments. Now that we're playing with other types in brw_fs.cpp, it's easy to trip over issues like these.
2010-09-04 21:28:04 -07:00
{
/* 6.32.38: mul */
if (src0.type == BRW_REGISTER_TYPE_D ||
src0.type == BRW_REGISTER_TYPE_UD ||
src1.type == BRW_REGISTER_TYPE_D ||
src1.type == BRW_REGISTER_TYPE_UD) {
assert(dest.type != BRW_REGISTER_TYPE_F);
}
if (src0.type == BRW_REGISTER_TYPE_F ||
(src0.file == BRW_IMMEDIATE_VALUE &&
src0.type == BRW_REGISTER_TYPE_VF)) {
assert(src1.type != BRW_REGISTER_TYPE_UD);
assert(src1.type != BRW_REGISTER_TYPE_D);
}
if (src1.type == BRW_REGISTER_TYPE_F ||
(src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_VF)) {
assert(src0.type != BRW_REGISTER_TYPE_UD);
assert(src0.type != BRW_REGISTER_TYPE_D);
}
assert(src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
src0.nr != BRW_ARF_ACCUMULATOR);
assert(src1.file != BRW_ARCHITECTURE_REGISTER_FILE ||
src1.nr != BRW_ARF_ACCUMULATOR);
return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1);
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965/eu: Emulate F32TO16 and F16TO32 on Broadwell. When we combine the Gen4-7 and Gen8+ generators, we'll need to handle half float packing/unpacking functions somehow. The Gen8+ generator code today just emulates the behavior of the Gen7 F32TO16/F16TO32 instructions, including the align16 mode bugs. Rather than messing with fs_generator/vec4_generator, I decided to just emulate the instructions at the brw_eu_emit.c layer. v2: Change gen >= 7 asserts to gen == 7 (suggested by Chris Forbes). Fix regressions on Haswell in VS tests due to type assertions. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-28 16:08:39 -07:00
brw_inst *
brw_F32TO16(struct brw_compile *p, struct brw_reg dst, struct brw_reg src)
{
const struct brw_context *brw = p->brw;
bool align16 = brw_inst_access_mode(brw, p->current) == BRW_ALIGN_16;
if (align16) {
assert(dst.type == BRW_REGISTER_TYPE_UD);
} else {
assert(dst.type == BRW_REGISTER_TYPE_W ||
dst.type == BRW_REGISTER_TYPE_UW ||
dst.type == BRW_REGISTER_TYPE_HF);
}
if (brw->gen >= 8) {
if (align16) {
/* Emulate the Gen7 zeroing bug (see comments in vec4_visitor's
* emit_pack_half_2x16 method.)
*/
brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
}
return brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_HF), src);
} else {
assert(brw->gen == 7);
return brw_alu1(p, BRW_OPCODE_F32TO16, dst, src);
}
}
brw_inst *
brw_F16TO32(struct brw_compile *p, struct brw_reg dst, struct brw_reg src)
{
const struct brw_context *brw = p->brw;
bool align16 = brw_inst_access_mode(brw, p->current) == BRW_ALIGN_16;
if (align16) {
assert(src.type == BRW_REGISTER_TYPE_UD);
} else {
assert(src.type == BRW_REGISTER_TYPE_W ||
src.type == BRW_REGISTER_TYPE_UW ||
src.type == BRW_REGISTER_TYPE_HF);
}
if (brw->gen >= 8) {
return brw_MOV(p, dst, retype(src, BRW_REGISTER_TYPE_HF));
} else {
assert(brw->gen == 7);
return brw_alu1(p, BRW_OPCODE_F16TO32, dst, src);
}
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
void brw_NOP(struct brw_compile *p)
{
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_NOP);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(p, insn, brw_imm_ud(0x0));
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
/***********************************************************************
* Comparisons, if/else/endif
*/
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
brw_JMPI(struct brw_compile *p, struct brw_reg index,
unsigned predicate_control)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Remove the dst and src0 parameters from brw_JMPI. In all cases, we set both dst and src0 to brw_ip_reg(). This is no accident: according to the ISA reference, both are required to be the IP register. So, we may as well drop the parameters. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-27 22:45:16 -07:00
struct brw_reg ip = brw_ip_reg();
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_exec_size(brw, inst, BRW_EXECUTE_2);
brw_inst_set_qtr_control(brw, inst, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(brw, inst, BRW_MASK_DISABLE);
brw_inst_set_pred_control(brw, inst, predicate_control);
i965: fixes for JMPI 1. the data type of <src1> (JMPI offset) must be D 2. execution size must be 1 3. NoMask 4. instruction compression isn't allowed.
2009-07-02 16:32:19 +08:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
return inst;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Move IF stack handling into the EU abstraction layer/brw_compile. This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 12:25:18 -07:00
static void
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
push_if_stack(struct brw_compile *p, brw_inst *inst)
i965: Move IF stack handling into the EU abstraction layer/brw_compile. This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 12:25:18 -07:00
{
i965: let the if_stack just store the instruction index If dynamic instruction store size is enabled, while after the brw_IF/ELSE() and before the brw_ENDIF() function, the eu instruction store base address(p->store) may change. Thus let if_stack just store the instruction index. This is somehow more flexible and safe than store the instruction memory address. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-12-21 14:51:59 +08:00
p->if_stack[p->if_stack_depth] = inst - p->store;
i965: Move IF stack handling into the EU abstraction layer/brw_compile. This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 12:25:18 -07:00
p->if_stack_depth++;
if (p->if_stack_array_size <= p->if_stack_depth) {
p->if_stack_array_size *= 2;
i965: let the if_stack just store the instruction index If dynamic instruction store size is enabled, while after the brw_IF/ELSE() and before the brw_ENDIF() function, the eu instruction store base address(p->store) may change. Thus let if_stack just store the instruction index. This is somehow more flexible and safe than store the instruction memory address. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-12-21 14:51:59 +08:00
p->if_stack = reralloc(p->mem_ctx, p->if_stack, int,
i965: Move IF stack handling into the EU abstraction layer/brw_compile. This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 12:25:18 -07:00
p->if_stack_array_size);
}
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
static brw_inst *
i965: let the if_stack just store the instruction index If dynamic instruction store size is enabled, while after the brw_IF/ELSE() and before the brw_ENDIF() function, the eu instruction store base address(p->store) may change. Thus let if_stack just store the instruction index. This is somehow more flexible and safe than store the instruction memory address. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-12-21 14:51:59 +08:00
pop_if_stack(struct brw_compile *p)
{
p->if_stack_depth--;
return &p->store[p->if_stack[p->if_stack_depth]];
}
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start. This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:13:32 -08:00
static void
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
push_loop_stack(struct brw_compile *p, brw_inst *inst)
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start. This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:13:32 -08:00
{
if (p->loop_stack_array_size < p->loop_stack_depth) {
p->loop_stack_array_size *= 2;
p->loop_stack = reralloc(p->mem_ctx, p->loop_stack, int,
p->loop_stack_array_size);
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop. The codegen backends all had this same tracking, so just do it at the EU level. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:44:41 -08:00
p->if_depth_in_loop = reralloc(p->mem_ctx, p->if_depth_in_loop, int,
p->loop_stack_array_size);
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start. This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:13:32 -08:00
}
p->loop_stack[p->loop_stack_depth] = inst - p->store;
p->loop_stack_depth++;
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop. The codegen backends all had this same tracking, so just do it at the EU level. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:44:41 -08:00
p->if_depth_in_loop[p->loop_stack_depth] = 0;
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start. This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:13:32 -08:00
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
static brw_inst *
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start. This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:13:32 -08:00
get_inner_do_insn(struct brw_compile *p)
{
return &p->store[p->loop_stack[p->loop_stack_depth - 1]];
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* EU takes the value from the flag register and pushes it onto some
* sort of a stack (presumably merging with any flag value already on
* the stack). Within an if block, the flags at the top of the stack
* control execution on each channel of the unit, eg. on each of the
* 16 pixel values in our wm programs.
*
* When the matching 'else' instruction is reached (presumably by
* countdown of the instruction count patched in by our ELSE/ENDIF
* functions), the relevent flags are inverted.
*
* When the matching 'endif' instruction is reached, the flags are
* popped off. If the stack is now empty, normal execution resumes.
*/
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
brw_IF(struct brw_compile *p, unsigned execute_size)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
insn = next_insn(p, BRW_OPCODE_IF);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* Override the defaults for this instruction:
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6) {
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_ip_reg());
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_imm_w(0));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen6_jump_count(brw, insn, 0);
i965 gen6+: Use 1-wide null operands for IF instructions The Sandy Bridge PRM, volume 4, part 2, section 5.3.10 ("5.3.10 Register Region Restrictions") contains the following restriction on the execution size and operand width of instructions: "3. ExecSize must be equal to or greater than Width." When emitting an IF instruction in single program flow mode on Gen6+, we use an ExecSize of 1, therefore the Width of each operand must also be 1. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-12-05 13:52:16 -08:00
brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src1(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
} else if (brw->gen == 7) {
i965 gen6+: Use 1-wide null operands for IF instructions The Sandy Bridge PRM, volume 4, part 2, section 5.3.10 ("5.3.10 Register Region Restrictions") contains the following restriction on the execution size and operand width of instructions: "3. ExecSize must be equal to or greater than Width." When emitting an IF instruction in single program flow mode on Gen6+, we use an ExecSize of 1, therefore the Width of each operand must also be 1. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-12-05 13:52:16 -08:00
brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
brw_set_src1(p, insn, brw_imm_ud(0));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, 0);
brw_inst_set_uip(brw, insn, 0);
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
} else {
brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(brw, insn, 0);
brw_inst_set_uip(brw, insn, 0);
i965: Fix up IF/ELSE/ENDIF for gen6. The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet).
2010-10-04 15:08:03 -07:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_exec_size(brw, insn, execute_size);
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
brw_inst_set_pred_control(brw, insn, BRW_PREDICATE_NORMAL);
brw_inst_set_mask_control(brw, insn, BRW_MASK_ENABLE);
i965: Don't set the "switch" flag on control flow instructions on Gen6+. Thread switching on control flow instructions is a documented workaround for Gen4-5 errata. As far as I can tell, it hasn't been needed since Sandybridge. Thread switching is not free, so in theory this may help performance slightly. Flow control instructions with the "switch" flag cannot be compacted, so removing it will make these instructions compactable. (Of course, we still have to implement compaction for flow control instructions...) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-12-12 18:01:00 -08:00
if (!p->single_program_flow && brw->gen < 6)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Move IF stack handling into the EU abstraction layer/brw_compile. This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 12:25:18 -07:00
push_if_stack(p, insn);
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop. The codegen backends all had this same tracking, so just do it at the EU level. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:44:41 -08:00
p->if_depth_in_loop[p->loop_stack_depth]++;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
return insn;
}
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
/* This function is only used for gen6-style IF instructions with an
* embedded comparison (conditional modifier). It is not used on gen7.
*/
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
i965: Make a brw_conditional_mod enum. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-06-29 17:50:20 -07:00
gen6_IF(struct brw_compile *p, enum brw_conditional_mod conditional,
i965: Rename brw_(IF|CONT)_gen6 functions to gen6_(IF|CONT).
2011-03-16 00:00:09 -07:00
struct brw_reg src0, struct brw_reg src1)
i965: Add EU emit support for gen6's new IF instruction with comparison.
2010-10-19 12:55:04 -07:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Add EU emit support for gen6's new IF instruction with comparison.
2010-10-19 12:55:04 -07:00
insn = next_insn(p, BRW_OPCODE_IF);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_imm_w(0));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_exec_size(brw, insn, p->compressed ? BRW_EXECUTE_16
: BRW_EXECUTE_8);
brw_inst_set_gen6_jump_count(brw, insn, 0);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
i965: Add EU emit support for gen6's new IF instruction with comparison.
2010-10-19 12:55:04 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_qtr_control(brw, insn) == BRW_COMPRESSION_NONE);
assert(brw_inst_pred_control(brw, insn) == BRW_PREDICATE_NONE);
brw_inst_set_cond_modifier(brw, insn, conditional);
i965: Add EU emit support for gen6's new IF instruction with comparison.
2010-10-19 12:55:04 -07:00
i965: Move IF stack handling into the EU abstraction layer/brw_compile. This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 12:25:18 -07:00
push_if_stack(p, insn);
i965: Add EU emit support for gen6's new IF instruction with comparison.
2010-10-19 12:55:04 -07:00
return insn;
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/**
* In single-program-flow (SPF) mode, convert IF and ELSE into ADDs.
*/
static void
convert_IF_ELSE_to_ADD(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *if_inst, brw_inst *else_inst)
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* The next instruction (where the ENDIF would be, if it existed) */
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *next_inst = &p->store[p->nr_insn];
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
assert(p->single_program_flow);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(if_inst != NULL && brw_inst_opcode(brw, if_inst) == BRW_OPCODE_IF);
assert(else_inst == NULL || brw_inst_opcode(brw, else_inst) == BRW_OPCODE_ELSE);
assert(brw_inst_exec_size(brw, if_inst) == BRW_EXECUTE_1);
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* Convert IF to an ADD instruction that moves the instruction pointer
* to the first instruction of the ELSE block. If there is no ELSE
* block, point to where ENDIF would be. Reverse the predicate.
*
* There's no need to execute an ENDIF since we don't need to do any
* stack operations, and if we're currently executing, we just want to
* continue normally.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_opcode(brw, if_inst, BRW_OPCODE_ADD);
brw_inst_set_pred_inv(brw, if_inst, true);
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
if (else_inst != NULL) {
/* Convert ELSE to an ADD instruction that points where the ENDIF
* would be.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_opcode(brw, else_inst, BRW_OPCODE_ADD);
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_imm_ud(brw, if_inst, (else_inst - if_inst + 1) * 16);
brw_inst_set_imm_ud(brw, else_inst, (next_inst - else_inst) * 16);
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_imm_ud(brw, if_inst, (next_inst - if_inst) * 16);
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
}
}
/**
* Patch IF and ELSE instructions with appropriate jump targets.
*/
static void
patch_IF_ELSE(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *if_inst, brw_inst *else_inst, brw_inst *endif_inst)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNG
2009-07-15 10:40:16 +08:00
i965: Only convert if/else to conditional adds prior to Gen6. Normally when outputting instructions in SPF (single program flow) mode, we convert IF and ELSE instructions to conditional ADD instructions applied to the IP register. On platforms prior to Gen6, flow control instructions cause an implied thread switch, so this is a significant savings. However, according to the SandyBridge PRM (Volume 4 part 2, p79): [Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by non-flow control instructions. So we have to disable this optimization on Gen6. On later platforms, there is no significant benefit to converting flow control instructions to ADDs, so for the sake of consistency, this patch disables the optimization on later platforms too. The reason we never noticed this problem before is that so far we haven't needed to use SPF mode on Gen6. However, later patches in this series will introduce a Gen6 GS program which uses SPF mode. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-11-24 21:41:07 -08:00
/* We shouldn't be patching IF and ELSE instructions in single program flow
* mode when gen < 6, because in single program flow mode on those
* platforms, we convert flow control instructions to conditional ADDs that
* operate on IP (see brw_ENDIF).
*
* However, on Gen6, writing to IP doesn't work in single program flow mode
* (see the SandyBridge PRM, Volume 4 part 2, p79: "When SPF is ON, IP may
* not be updated by non-flow control instructions."). And on later
* platforms, there is no significant benefit to converting control flow
* instructions to conditional ADDs. So we do patch IF and ELSE
* instructions in single program flow mode on those platforms.
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6)
i965: Only convert if/else to conditional adds prior to Gen6. Normally when outputting instructions in SPF (single program flow) mode, we convert IF and ELSE instructions to conditional ADD instructions applied to the IP register. On platforms prior to Gen6, flow control instructions cause an implied thread switch, so this is a significant savings. However, according to the SandyBridge PRM (Volume 4 part 2, p79): [Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by non-flow control instructions. So we have to disable this optimization on Gen6. On later platforms, there is no significant benefit to converting flow control instructions to ADDs, so for the sake of consistency, this patch disables the optimization on later platforms too. The reason we never noticed this problem before is that so far we haven't needed to use SPF mode on Gen6. However, later patches in this series will introduce a Gen6 GS program which uses SPF mode. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-11-24 21:41:07 -08:00
assert(!p->single_program_flow);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(if_inst != NULL && brw_inst_opcode(brw, if_inst) == BRW_OPCODE_IF);
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
assert(endif_inst != NULL);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(else_inst == NULL || brw_inst_opcode(brw, else_inst) == BRW_OPCODE_ELSE);
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
i965/eu: Refactor jump distance scaling to use a helper function. Different generations of hardware measure jump distances in different units. Previously, every function that needed to set a jump target open coded this scaling, or made a hardcoded assumption (i.e. just used 2). Most functions start with the number of instructions to jump, and scale up to the hardware-specific value. So, I made the function match that. Others start with a byte offset, and divide by a constant (8) to obtain the jump distance. This is actually 16 / 2 (the jump scale for Gen5-7). v2: Make the helper a static inline defined in brw_eu.h, instead of an actual function in brw_eu_emit.c (as suggested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:00:25 -07:00
unsigned br = brw_jump_scale(brw);
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_opcode(brw, endif_inst) == BRW_OPCODE_ENDIF);
brw_inst_set_exec_size(brw, endif_inst, brw_inst_exec_size(brw, if_inst));
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
if (else_inst == NULL) {
/* Patch IF -> ENDIF */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6) {
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* Turn it into an IFF, which means no mask stack operations for
* all-false and jumping past the ENDIF.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_opcode(brw, if_inst, BRW_OPCODE_IFF);
brw_inst_set_gen4_jump_count(brw, if_inst,
br * (endif_inst - if_inst + 1));
brw_inst_set_gen4_pop_count(brw, if_inst, 0);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* As of gen6, there is no IFF and IF must point to the ENDIF. */
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen6_jump_count(brw, if_inst, br*(endif_inst - if_inst));
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_uip(brw, if_inst, br * (endif_inst - if_inst));
brw_inst_set_jip(brw, if_inst, br * (endif_inst - if_inst));
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
}
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_exec_size(brw, else_inst, brw_inst_exec_size(brw, if_inst));
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* Patch IF -> ELSE */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen4_jump_count(brw, if_inst,
br * (else_inst - if_inst));
brw_inst_set_gen4_pop_count(brw, if_inst, 0);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen6_jump_count(brw, if_inst,
br * (else_inst - if_inst + 1));
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
}
/* Patch ELSE -> ENDIF */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6) {
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* BRW_OPCODE_ELSE pre-gen6 should point just past the
* matching ENDIF.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen4_jump_count(brw, else_inst,
br * (endif_inst - else_inst + 1));
brw_inst_set_gen4_pop_count(brw, else_inst, 1);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* BRW_OPCODE_ELSE on gen6 should point to the matching ENDIF. */
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen6_jump_count(brw, else_inst,
br * (endif_inst - else_inst));
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
} else {
/* The IF instruction's JIP should point just past the ELSE */
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, if_inst, br * (else_inst - if_inst + 1));
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
/* The IF instruction's UIP and ELSE's JIP should point to ENDIF */
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_uip(brw, if_inst, br * (endif_inst - if_inst));
brw_inst_set_jip(brw, else_inst, br * (endif_inst - else_inst));
i965/eu: Set UIP on ELSE instructions on Broadwell. Broadwell adds UIP on ELSE instructions. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:05:42 -07:00
if (brw->gen >= 8) {
/* Since we don't set branch_ctrl, the ELSE's JIP and UIP both
* should point to ENDIF.
*/
brw_inst_set_uip(brw, else_inst, br * (endif_inst - else_inst));
}
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
}
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
}
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
}
void
brw_ELSE(struct brw_compile *p)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
insn = next_insn(p, BRW_OPCODE_ELSE);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6) {
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_ip_reg());
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_imm_w(0));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen6_jump_count(brw, insn, 0);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
} else if (brw->gen == 7) {
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_ud(0));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, 0);
brw_inst_set_uip(brw, insn, 0);
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
} else {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(brw, insn, 0);
brw_inst_set_uip(brw, insn, 0);
i965: Fix up IF/ELSE/ENDIF for gen6. The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet).
2010-10-04 15:08:03 -07:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(brw, insn, BRW_MASK_ENABLE);
i965: Don't set the "switch" flag on control flow instructions on Gen6+. Thread switching on control flow instructions is a documented workaround for Gen4-5 errata. As far as I can tell, it hasn't been needed since Sandybridge. Thread switching is not free, so in theory this may help performance slightly. Flow control instructions with the "switch" flag cannot be compacted, so removing it will make these instructions compactable. (Of course, we still have to implement compaction for flow control instructions...) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-12-12 18:01:00 -08:00
if (!p->single_program_flow && brw->gen < 6)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
push_if_stack(p, insn);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Move IF stack handling into the EU abstraction layer/brw_compile. This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 12:25:18 -07:00
void
brw_ENDIF(struct brw_compile *p)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = NULL;
brw_inst *else_inst = NULL;
brw_inst *if_inst = NULL;
brw_inst *tmp;
i965: call next_insn() before referencing a instruction by index A single next_insn may change the base address of instruction store memory(p->store), so call it first before referencing the instruction store pointer from an index. This the final prepare work to enable the dynamic store size. v2: comments from Ken, define emit_endif as bool type Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:32:02 +08:00
bool emit_endif = true;
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
i965: Only convert if/else to conditional adds prior to Gen6. Normally when outputting instructions in SPF (single program flow) mode, we convert IF and ELSE instructions to conditional ADD instructions applied to the IP register. On platforms prior to Gen6, flow control instructions cause an implied thread switch, so this is a significant savings. However, according to the SandyBridge PRM (Volume 4 part 2, p79): [Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by non-flow control instructions. So we have to disable this optimization on Gen6. On later platforms, there is no significant benefit to converting flow control instructions to ADDs, so for the sake of consistency, this patch disables the optimization on later platforms too. The reason we never noticed this problem before is that so far we haven't needed to use SPF mode on Gen6. However, later patches in this series will introduce a Gen6 GS program which uses SPF mode. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-11-24 21:41:07 -08:00
/* In single program flow mode, we can express IF and ELSE instructions
* equivalently as ADD instructions that operate on IP. On platforms prior
* to Gen6, flow control instructions cause an implied thread switch, so
* this is a significant savings.
*
* However, on Gen6, writing to IP doesn't work in single program flow mode
* (see the SandyBridge PRM, Volume 4 part 2, p79: "When SPF is ON, IP may
* not be updated by non-flow control instructions."). And on later
* platforms, there is no significant benefit to converting control flow
* instructions to conditional ADDs. So we only do this trick on Gen4 and
* Gen5.
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6 && p->single_program_flow)
i965: call next_insn() before referencing a instruction by index A single next_insn may change the base address of instruction store memory(p->store), so call it first before referencing the instruction store pointer from an index. This the final prepare work to enable the dynamic store size. v2: comments from Ken, define emit_endif as bool type Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:32:02 +08:00
emit_endif = false;
/*
* A single next_insn() may change the base adress of instruction store
* memory(p->store), so call it first before referencing the instruction
* store pointer from an index
*/
if (emit_endif)
insn = next_insn(p, BRW_OPCODE_ENDIF);
/* Pop the IF and (optional) ELSE instructions from the stack */
p->if_depth_in_loop[p->loop_stack_depth]--;
tmp = pop_if_stack(p);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_opcode(brw, tmp) == BRW_OPCODE_ELSE) {
i965: call next_insn() before referencing a instruction by index A single next_insn may change the base address of instruction store memory(p->store), so call it first before referencing the instruction store pointer from an index. This the final prepare work to enable the dynamic store size. v2: comments from Ken, define emit_endif as bool type Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:32:02 +08:00
else_inst = tmp;
tmp = pop_if_stack(p);
}
if_inst = tmp;
if (!emit_endif) {
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* ENDIF is useless; don't bother emitting it. */
convert_IF_ELSE_to_ADD(p, if_inst, else_inst);
return;
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6) {
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(p, insn, brw_imm_d(0x0));
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
brw_set_dest(p, insn, brw_imm_w(0));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
} else if (brw->gen == 7) {
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_ud(0));
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
} else {
brw_set_src0(p, insn, brw_imm_d(0));
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
}
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(brw, insn, BRW_MASK_ENABLE);
i965: Don't set the "switch" flag on control flow instructions on Gen6+. Thread switching on control flow instructions is a documented workaround for Gen4-5 errata. As far as I can tell, it hasn't been needed since Sandybridge. Thread switching is not free, so in theory this may help performance slightly. Flow control instructions with the "switch" flag cannot be compacted, so removing it will make these instructions compactable. (Of course, we still have to implement compaction for flow control instructions...) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-12-12 18:01:00 -08:00
if (brw->gen < 6)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
/* Also pop item off the stack in the endif instruction: */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen4_jump_count(brw, insn, 0);
brw_inst_set_gen4_pop_count(brw, insn, 1);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
} else if (brw->gen == 6) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen6_jump_count(brw, insn, 2);
i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge. Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-03-15 23:53:40 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, 2);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Rework IF/ELSE jump target back-patching. The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-16 13:40:00 -07:00
patch_IF_ELSE(p, if_inst, else_inst, insn);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
brw_BREAK(struct brw_compile *p)
support branch and loop in pixel shader most of the sample working with some small modification
2007-06-21 10:22:28 +08:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
support branch and loop in pixel shader most of the sample working with some small modification
2007-06-21 10:22:28 +08:00
insn = next_insn(p, BRW_OPCODE_BREAK);
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
if (brw->gen >= 8) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, brw_imm_d(0x0));
} else if (brw->gen >= 6) {
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_d(0x0));
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
} else {
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_ip_reg());
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen4_pop_count(brw, insn,
p->if_depth_in_loop[p->loop_stack_depth]);
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
i965: Set ExecSize to 16 for loop instructions in SIMD16 shaders. Previously, we explicitly set the execution size to BRW_EXECUTE_8 and disabled compression for loop instructions. I can't imagine how this could be correct in SIMD16 mode. Looking at the history, it appears that this code has used BRW_EXECUTE_8 since 2007, when we had a SIMD8 backend that supported control flow and a separate SIMD16 backend that didn't. Presumably, when we added SIMD16 support for shaders with control flow, we simply neglected to update it. Note that Gen4-5 don't support SIMD16 on shaders with control flow. This might be a candidate for stable, but would need to be rewritten completely due to the brw_inst API changes in master. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-04 00:06:05 -07:00
brw_inst_set_exec_size(brw, insn, p->compressed ? BRW_EXECUTE_16
: BRW_EXECUTE_8);
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
support continue, fix conditional
2007-09-29 15:00:52 +08:00
return insn;
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
i965/eu: Merge brw_CONT and gen6_CONT. The only difference is setting PopCount on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-04 14:26:26 -07:00
brw_CONT(struct brw_compile *p)
i965: Add support for gen6 CONTINUE instruction emit. At this point, piglit tests for fragment shader loops are working.
2010-12-01 14:02:14 -08:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Add support for gen6 CONTINUE instruction emit. At this point, piglit tests for fragment shader loops are working.
2010-12-01 14:02:14 -08:00
insn = next_insn(p, BRW_OPCODE_CONTINUE);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_ip_reg());
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
if (brw->gen >= 8) {
brw_set_src0(p, insn, brw_imm_d(0x0));
} else {
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0x0));
}
i965: Add support for gen6 CONTINUE instruction emit. At this point, piglit tests for fragment shader loops are working.
2010-12-01 14:02:14 -08:00
i965/eu: Merge brw_CONT and gen6_CONT. The only difference is setting PopCount on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-04 14:26:26 -07:00
if (brw->gen < 6) {
brw_inst_set_gen4_pop_count(brw, insn,
p->if_depth_in_loop[p->loop_stack_depth]);
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
i965: Set ExecSize to 16 for loop instructions in SIMD16 shaders. Previously, we explicitly set the execution size to BRW_EXECUTE_8 and disabled compression for loop instructions. I can't imagine how this could be correct in SIMD16 mode. Looking at the history, it appears that this code has used BRW_EXECUTE_8 since 2007, when we had a SIMD8 backend that supported control flow and a separate SIMD16 backend that didn't. Presumably, when we added SIMD16 support for shaders with control flow, we simply neglected to update it. Note that Gen4-5 don't support SIMD16 on shaders with control flow. This might be a candidate for stable, but would need to be rewritten completely due to the brw_inst API changes in master. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-04 00:06:05 -07:00
brw_inst_set_exec_size(brw, insn, p->compressed ? BRW_EXECUTE_16
: BRW_EXECUTE_8);
support branch and loop in pixel shader most of the sample working with some small modification
2007-06-21 10:22:28 +08:00
return insn;
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
gen6_HALT(struct brw_compile *p)
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
insn = next_insn(p, BRW_OPCODE_HALT);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
if (brw->gen >= 8) {
brw_set_src0(p, insn, brw_imm_d(0x0));
} else {
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_d(0x0)); /* UIP and JIP, updated later. */
}
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
if (p->compressed) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_16);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_8);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
}
return insn;
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* DO/WHILE loop:
i965: Add support for gen6 DO/WHILE ISA emit. There's no more DO since there's no more mask stack, and WHILE has been shuffled like IF was.
2010-12-01 10:45:52 -08:00
*
* The DO/WHILE is just an unterminated loop -- break or continue are
* used for control within the loop. We have a few ways they can be
* done.
*
* For uniform control flow, the WHILE is just a jump, so ADD ip, ip,
* jip and no DO instruction.
*
* For non-uniform control flow pre-gen6, there's a DO instruction to
* push the mask, and a WHILE to jump back, and BREAK to get out and
* pop the mask.
*
* For gen6, there's no more mask stack, so no need for DO. WHILE
* just points back to the first instruction of the loop.
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
*/
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
brw_DO(struct brw_compile *p, unsigned execute_size)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Add support for gen6 DO/WHILE ISA emit. There's no more DO since there's no more mask stack, and WHILE has been shuffled like IF was.
2010-12-01 10:45:52 -08:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6 || p->single_program_flow) {
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start. This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:13:32 -08:00
push_loop_stack(p, &p->store[p->nr_insn]);
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
return &p->store[p->nr_insn];
} else {
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_DO);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start. This is a similar cleanup to what we did for brw_IF(), brw_ELSE(), brw_ENDIF() handling. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:13:32 -08:00
push_loop_stack(p, insn);
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
/* Override the defaults for this instruction:
*/
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_null_reg());
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_null_reg());
brw_set_src1(p, insn, brw_null_reg());
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
brw_inst_set_exec_size(brw, insn, execute_size);
brw_inst_set_pred_control(brw, insn, BRW_PREDICATE_NONE);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
return insn;
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:30:03 -08:00
/**
* For pre-gen6, we patch BREAK/CONT instructions to point at the WHILE
* instruction here.
*
* For gen6+, see brw_set_uip_jip(), which doesn't care so much about the loop
* nesting, since it can always just point to the end of the block/current loop.
*/
static void
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_patch_break_cont(struct brw_compile *p, brw_inst *while_inst)
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:30:03 -08:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *do_inst = get_inner_do_insn(p);
brw_inst *inst;
i965/eu: Refactor jump distance scaling to use a helper function. Different generations of hardware measure jump distances in different units. Previously, every function that needed to set a jump target open coded this scaling, or made a hardcoded assumption (i.e. just used 2). Most functions start with the number of instructions to jump, and scale up to the hardware-specific value. So, I made the function match that. Others start with a byte offset, and divide by a constant (8) to obtain the jump distance. This is actually 16 / 2 (the jump scale for Gen5-7). v2: Make the helper a static inline defined in brw_eu.h, instead of an actual function in brw_eu_emit.c (as suggested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:00:25 -07:00
unsigned br = brw_jump_scale(brw);
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:30:03 -08:00
i965/eu: Make it clear that brw_patch_break_count only runs on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 09:22:27 -07:00
assert(brw->gen < 6);
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:30:03 -08:00
for (inst = while_inst - 1; inst != do_inst; inst--) {
/* If the jump count is != 0, that means that this instruction has already
* been patched because it's part of a loop inside of the one we're
* patching.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_opcode(brw, inst) == BRW_OPCODE_BREAK &&
brw_inst_gen4_jump_count(brw, inst) == 0) {
brw_inst_set_gen4_jump_count(brw, inst, br*((while_inst - inst) + 1));
} else if (brw_inst_opcode(brw, inst) == BRW_OPCODE_CONTINUE &&
brw_inst_gen4_jump_count(brw, inst) == 0) {
brw_inst_set_gen4_jump_count(brw, inst, br * (while_inst - inst));
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:30:03 -08:00
}
}
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *
brw_WHILE(struct brw_compile *p)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn, *do_insn;
i965/eu: Refactor jump distance scaling to use a helper function. Different generations of hardware measure jump distances in different units. Previously, every function that needed to set a jump target open coded this scaling, or made a hardcoded assumption (i.e. just used 2). Most functions start with the number of instructions to jump, and scale up to the hardware-specific value. So, I made the function match that. Others start with a byte offset, and divide by a constant (8) to obtain the jump distance. This is actually 16 / 2 (the jump scale for Gen5-7). v2: Make the helper a static inline defined in brw_eu.h, instead of an actual function in brw_eu_emit.c (as suggested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:00:25 -07:00
unsigned br = brw_jump_scale(brw);
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
i965/eu: Refactor brw_WHILE to share a bit more code on Gen6+. We're going to add a Gen8+ case shortly, which would need to duplicate this code again. Instead, share it. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:06:36 -07:00
if (brw->gen >= 6) {
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
insn = next_insn(p, BRW_OPCODE_WHILE);
i965: call next_insn() before referencing a instruction by index A single next_insn may change the base address of instruction store memory(p->store), so call it first before referencing the instruction store pointer from an index. This the final prepare work to enable the dynamic store size. v2: comments from Ken, define emit_endif as bool type Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:32:02 +08:00
do_insn = get_inner_do_insn(p);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965/eu: Set src0 file to IMM on Gen8+ flow control instructions. According to the documentation, we need to set the source 0 register type to IMM for flow control instructinos that have both JIP and UIP. Out of paranoia, just make all flow control instructions use IMM; there's no benefit to using ARF anyway, and it could trouble that's difficult to diagnose. See commit 9584959123b0453cf5313722357e3abb9f736aa7, which did the analogous change in the gen8_generator code. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:10:55 -07:00
if (brw->gen >= 8) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(brw, insn, br * (do_insn - insn));
} else if (brw->gen == 7) {
i965/eu: Refactor brw_WHILE to share a bit more code on Gen6+. We're going to add a Gen8+ case shortly, which would need to duplicate this code again. Instead, share it. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 07:06:36 -07:00
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_ud(0));
brw_inst_set_jip(brw, insn, br * (do_insn - insn));
} else {
brw_set_dest(p, insn, brw_imm_w(0));
brw_inst_set_gen6_jump_count(brw, insn, br * (do_insn - insn));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Set ExecSize to 16 for loop instructions in SIMD16 shaders. Previously, we explicitly set the execution size to BRW_EXECUTE_8 and disabled compression for loop instructions. I can't imagine how this could be correct in SIMD16 mode. Looking at the history, it appears that this code has used BRW_EXECUTE_8 since 2007, when we had a SIMD8 backend that supported control flow and a separate SIMD16 backend that didn't. Presumably, when we added SIMD16 support for shaders with control flow, we simply neglected to update it. Note that Gen4-5 don't support SIMD16 on shaders with control flow. This might be a candidate for stable, but would need to be rewritten completely due to the brw_inst API changes in master. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-04 00:06:05 -07:00
brw_inst_set_exec_size(brw, insn, p->compressed ? BRW_EXECUTE_16
: BRW_EXECUTE_8);
i965: Add support for gen6 DO/WHILE ISA emit. There's no more DO since there's no more mask stack, and WHILE has been shuffled like IF was.
2010-12-01 10:45:52 -08:00
} else {
if (p->single_program_flow) {
insn = next_insn(p, BRW_OPCODE_ADD);
i965: call next_insn() before referencing a instruction by index A single next_insn may change the base address of instruction store memory(p->store), so call it first before referencing the instruction store pointer from an index. This the final prepare work to enable the dynamic store size. v2: comments from Ken, define emit_endif as bool type Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:32:02 +08:00
do_insn = get_inner_do_insn(p);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_ip_reg());
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d((do_insn - insn) * 16));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_1);
i965: Add support for gen6 DO/WHILE ISA emit. There's no more DO since there's no more mask stack, and WHILE has been shuffled like IF was.
2010-12-01 10:45:52 -08:00
} else {
insn = next_insn(p, BRW_OPCODE_WHILE);
i965: call next_insn() before referencing a instruction by index A single next_insn may change the base address of instruction store memory(p->store), so call it first before referencing the instruction store pointer from an index. This the final prepare work to enable the dynamic store size. v2: comments from Ken, define emit_endif as bool type Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-12-21 15:32:02 +08:00
do_insn = get_inner_do_insn(p);
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_opcode(brw, do_insn) == BRW_OPCODE_DO);
i965: Avoid branch instructions while in single program flow mode. There is an errata for Broadwater that threads don't have the instruction/loop mask stacks initialized on thread spawn. In single program flow mode, those stacks are not writable, so we can't initialize them. However, they do get read during ELSE and ENDIF instructions. So, instead, replace branch instructions in single program flow mode with predicated jumps (ADD to the ip register), avoiding use of the more complicated branch instructions that may fail. This is also a minor optimization as no ENDIF equivalent is necessary. Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-10-18 00:24:01 -07:00
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, brw_ip_reg());
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_ip_reg());
brw_set_src1(p, insn, brw_imm_d(0));
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_exec_size(brw, insn, brw_inst_exec_size(brw, do_insn));
brw_inst_set_gen4_jump_count(brw, insn, br * (do_insn - insn + 1));
brw_inst_set_gen4_pop_count(brw, insn, 0);
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:30:03 -08:00
brw_patch_break_cont(p, insn);
i965: Add support for gen6 DO/WHILE ISA emit. There's no more DO since there's no more mask stack, and WHILE has been shuffled like IF was.
2010-12-01 10:45:52 -08:00
}
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 12:30:03 -08:00
p->loop_stack_depth--;
support branch and loop in pixel shader most of the sample working with some small modification
2007-06-21 10:22:28 +08:00
return insn;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
Revert "i965: Move brw_land_fwd_jump() to compilation unit of its use." This reverts commit f3cb2e6ed7059b22752a6b7d7a98c07ba6b5552e. brw_land_fwd_jump() is convenient wherever we produce JMPI instructions and we will use JMPI to implement framebuffer writes that involve line antialiasing in gen < 6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 15:03:07 +02:00
/* FORWARD JUMPS:
*/
void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx)
{
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *jmp_insn = &p->store[jmp_insn_idx];
Revert "i965: Move brw_land_fwd_jump() to compilation unit of its use." This reverts commit f3cb2e6ed7059b22752a6b7d7a98c07ba6b5552e. brw_land_fwd_jump() is convenient wherever we produce JMPI instructions and we will use JMPI to implement framebuffer writes that involve line antialiasing in gen < 6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 15:03:07 +02:00
unsigned jmpi = 1;
if (brw->gen >= 5)
jmpi = 2;
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_opcode(brw, jmp_insn) == BRW_OPCODE_JMPI);
assert(brw_inst_src1_reg_file(brw, jmp_insn) == BRW_IMMEDIATE_VALUE);
Revert "i965: Move brw_land_fwd_jump() to compilation unit of its use." This reverts commit f3cb2e6ed7059b22752a6b7d7a98c07ba6b5552e. brw_land_fwd_jump() is convenient wherever we produce JMPI instructions and we will use JMPI to implement framebuffer writes that involve line antialiasing in gen < 6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 15:03:07 +02:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_gen4_jump_count(brw, jmp_insn,
jmpi * (p->nr_insn - jmp_insn_idx - 1));
Revert "i965: Move brw_land_fwd_jump() to compilation unit of its use." This reverts commit f3cb2e6ed7059b22752a6b7d7a98c07ba6b5552e. brw_land_fwd_jump() is convenient wherever we produce JMPI instructions and we will use JMPI to implement framebuffer writes that involve line antialiasing in gen < 6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 15:03:07 +02:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
/* To integrate with the above, it makes sense that the comparison
* instruction should populate the flag register. It might be simpler
* just to use the flag reg for most WM tasks?
*/
void brw_CMP(struct brw_compile *p,
struct brw_reg dest,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned conditional,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
struct brw_reg src0,
struct brw_reg src1)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_CMP);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965/eu: Port Broadwell CMP destination type hack to brw_eu_emit.c. See gen8_generator::CMP(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 07:51:51 -07:00
if (brw->gen >= 8) {
/* The CMP instruction appears to behave erratically for floating point
* sources unless the destination type is also float. Overriding it to
* match src0 makes it work in all cases.
*/
dest.type = src0.type;
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_cond_modifier(brw, insn, conditional);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Implement work-around for CMP with null dest on Haswell. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-15 14:59:09 -07:00
/* Item WaCMPInstNullDstForcesThreadSwitch in the Haswell Bspec workarounds
* page says:
* "Any CMP instruction with a null destination must use a {switch}."
i965: Apply CMP NULL {Switch} work-around to other Gen7s. Listed in the restrictions section of CMP, but not on the work-arounds page. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-21 00:18:11 -07:00
*
* It also applies to other Gen7 platforms (IVB, BYT) even though it isn't
* mentioned on their work-arounds pages.
i965: Implement work-around for CMP with null dest on Haswell. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-15 14:59:09 -07:00
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen == 7) {
i965: Implement work-around for CMP with null dest on Haswell. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-15 14:59:09 -07:00
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == BRW_ARF_NULL) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_thread_control(brw, insn, BRW_THREAD_SWITCH);
i965: Implement work-around for CMP with null dest on Haswell. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-15 14:59:09 -07:00
}
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
/***********************************************************************
* Helpers for the various SEND message types:
*/
i965: new and updated comments
2009-03-31 10:49:41 -06:00
/** Extended math function, float[8].
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
*/
i965: Rename brw_math to gen4_math. Usually, I try to use "brw" for functions that apply to all generations, and "gen4" for dead end/legacy code that is only used on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 02:12:46 -07:00
void gen4_math(struct brw_compile *p,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
struct brw_reg dest,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned function,
unsigned msg_reg_nr,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
struct brw_reg src,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned data_type,
unsigned precision )
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 01:56:12 -07:00
assert(brw->gen < 6);
i965: Add SNB math opcode support. This is untested at this point.
2010-02-24 09:16:19 -08:00
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 01:56:12 -07:00
/* Example code doesn't set predicate_control for send
* instructions.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_pred_control(brw, insn, 0);
brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
i965: Fix message and response length calculations for INT DIV. Both POW and INT DIV need a message length of 2; previously, we only checked for POW. Also, BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER has a response length of 2; previously, we only checked for SINCOS. We don't use this message, but in case we ever decide to, we may as well fix it now. While we're at it, just move these computations into brw_set_math_message, since they're entirely based on the function. This fixes it for both brw_math and the old backend's brw_math_16. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-28 17:37:52 -07:00
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 01:56:12 -07:00
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src);
brw_set_math_message(p,
insn,
function,
src.type == BRW_REGISTER_TYPE_D,
precision,
data_type);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 01:56:12 -07:00
void gen6_math(struct brw_compile *p,
i965: Add support for POW in gen6 FS. Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
2010-08-22 01:33:57 -07:00
struct brw_reg dest,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned function,
i965: Add support for POW in gen6 FS. Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
2010-08-22 01:33:57 -07:00
struct brw_reg src0,
struct brw_reg src1)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_MATH);
i965: Add support for POW in gen6 FS. Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
2010-08-22 01:33:57 -07:00
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 01:56:12 -07:00
assert(brw->gen >= 6);
i965/gen7: Relax restrictions on fake MRFs Gen6 has write-only MRF registers, and for ease of implementation we paritition off 16 general purposes registers to act as MRFs on Gen7. Knowing that our Gen7 MRFs are actually GRFs, we can do things we can't do with real MRFs: - read from them; - return values directly to them from a send instruction; and - compute directly to them with math instructions. Reviewed-by: Eric Anholt <eric@anholt.net>
2013-02-11 11:06:13 -08:00
assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
(brw->gen >= 7 && dest.file == BRW_MESSAGE_REGISTER_FILE));
i965/eu: Allow math on immediates on Broadwell. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-07-11 15:54:11 -07:00
assert(src0.file == BRW_GENERAL_REGISTER_FILE ||
(brw->gen >= 8 && src0.file == BRW_IMMEDIATE_VALUE));
i965: Add a couple of checks for gen6 math instruction limits.
2010-10-11 13:30:12 -07:00
assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen == 6) {
i965: Enable faster workaround-free math on Ivybridge. According to the documentation, Ivybridge's math instruction works in SIMD16 mode for the fragment shader, and no longer forbids align16 mode for the vertex shader. The documentation claims that SIMD16 mode isn't supported for INT DIV, but empirical evidence shows that it works fine. Presumably the note is trying to warn us that the variant that returns both quotient and remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1 would be sechalf(dst), trashing half your results. Since we don't use that variant, we don't care and can just enable SIMD16 everywhere. The documentation also still claims that source modifiers and conditional modifiers aren't supported, but empirical evidence and study of the simulator both show that they work just fine. Goodbye workarounds. Math just works now. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-10-18 12:24:47 -07:00
assert(src0.hstride == BRW_HORIZONTAL_STRIDE_1);
assert(src1.hstride == BRW_HORIZONTAL_STRIDE_1);
}
i965: Add a couple of checks for gen6 math instruction limits.
2010-10-11 13:30:12 -07:00
i965: Fix assertions about register types for INT DIV in brw_math. BRW_MATH_FUNCTION_REMAINDER was missing. Also, it seems worthwhile to assert that INT DIV's arguments are signed/unsigned integers. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-28 17:37:51 -07:00
if (function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT ||
function == BRW_MATH_FUNCTION_INT_DIV_REMAINDER ||
function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
assert(src0.type != BRW_REGISTER_TYPE_F);
assert(src1.type != BRW_REGISTER_TYPE_F);
i965/eu: Allow math on immediates on Broadwell. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-07-11 15:54:11 -07:00
assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
(brw->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
i965: Fix assertions about register types for INT DIV in brw_math. BRW_MATH_FUNCTION_REMAINDER was missing. Also, it seems worthwhile to assert that INT DIV's arguments are signed/unsigned integers. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-28 17:37:51 -07:00
} else {
i965: Add a couple of checks for gen6 math instruction limits.
2010-10-11 13:30:12 -07:00
assert(src0.type == BRW_REGISTER_TYPE_F);
assert(src1.type == BRW_REGISTER_TYPE_F);
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 01:56:12 -07:00
if (function == BRW_MATH_FUNCTION_POW) {
i965/eu: Allow math on immediates on Broadwell. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-07-11 15:54:11 -07:00
assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
(brw->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 01:56:12 -07:00
} else {
assert(src1.file == BRW_ARCHITECTURE_REGISTER_FILE &&
src1.nr == BRW_ARF_NULL);
}
i965: Add a couple of checks for gen6 math instruction limits.
2010-10-11 13:30:12 -07:00
}
i965: Enable faster workaround-free math on Ivybridge. According to the documentation, Ivybridge's math instruction works in SIMD16 mode for the fragment shader, and no longer forbids align16 mode for the vertex shader. The documentation claims that SIMD16 mode isn't supported for INT DIV, but empirical evidence shows that it works fine. Presumably the note is trying to warn us that the variant that returns both quotient and remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1 would be sechalf(dst), trashing half your results. Since we don't use that variant, we don't care and can just enable SIMD16 everywhere. The documentation also still claims that source modifiers and conditional modifiers aren't supported, but empirical evidence and study of the simulator both show that they work just fine. Goodbye workarounds. Math just works now. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-10-18 12:24:47 -07:00
/* Source modifiers are ignored for extended math instructions on Gen6. */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen == 6) {
i965: Enable faster workaround-free math on Ivybridge. According to the documentation, Ivybridge's math instruction works in SIMD16 mode for the fragment shader, and no longer forbids align16 mode for the vertex shader. The documentation claims that SIMD16 mode isn't supported for INT DIV, but empirical evidence shows that it works fine. Presumably the note is trying to warn us that the variant that returns both quotient and remainder in (dst, dst + 1) doesn't work in SIMD16 mode since dst + 1 would be sechalf(dst), trashing half your results. Since we don't use that variant, we don't care and can just enable SIMD16 everywhere. The documentation also still claims that source modifiers and conditional modifiers aren't supported, but empirical evidence and study of the simulator both show that they work just fine. Goodbye workarounds. Math just works now. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-10-18 12:24:47 -07:00
assert(!src0.negate);
assert(!src0.abs);
assert(!src1.negate);
assert(!src1.abs);
}
i965: Work around gen6 ignoring source modifiers on math instructions. With the change of extended math from having the arguments moved into mrfs and handed off through message passing to being directly hooked up to the EU, it looks like the piece for doing source modifiers (negate and abs) was left out. Fixes: fog-modes glean/fp1-ARB_fog_exp test glean/fp1-ARB_fog_exp2 test glean/fp1-Computed fog exp test glean/fp1-Computed fog exp2 test ext_fog_coord-modes
2010-12-07 14:50:50 -08:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_math_function(brw, insn, function);
i965: Add support for POW in gen6 FS. Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
2010-08-22 01:33:57 -07:00
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
i965: Add support for POW in gen6 FS. Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
2010-08-22 01:33:57 -07:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: new and updated comments
2009-03-31 10:49:41 -06:00
/**
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
* Write a block of OWORDs (half a GRF each) from the scratch buffer,
* using a constant offset per channel.
*
* The offset must be aligned to oword size (16 bytes). Used for
* register spilling.
i965: new and updated comments
2009-03-31 10:49:41 -06:00
*/
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
void brw_oword_block_write_scratch(struct brw_compile *p,
struct brw_reg mrf,
int num_regs,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned offset)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
uint32_t msg_control, msg_type;
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
int mlen;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6)
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
offset /= 16;
i965: Don't emit register spill offsets directly into g0. g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21 14:40:49 -07:00
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
if (num_regs == 1) {
msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
mlen = 2;
} else {
msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
mlen = 3;
}
i965: Don't emit register spill offsets directly into g0. g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21 14:40:49 -07:00
/* Set up the message header. This is g0, with g0.2 filled with
* the offset. We don't want to leave our offset around in g0 or
* it'll screw up texture samples, so set it up inside the message
* reg.
*/
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 16:57:02 -07:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Don't emit register spill offsets directly into g0. g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21 14:40:49 -07:00
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
i965: new and updated comments
2009-03-31 10:49:41 -06:00
/* set message header global offset field (reg 0, element 2) */
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
brw_MOV(p,
i965: Don't emit register spill offsets directly into g0. g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21 14:40:49 -07:00
retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
mrf.nr,
2), BRW_REGISTER_TYPE_UD),
brw_imm_ud(offset));
i965: fix fetching constants from constant buffer in glsl path the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
2009-06-26 20:38:07 +02:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
brw_pop_insn_state(p);
}
{
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
struct brw_reg dest;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
int send_commit_msg;
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
struct brw_reg src_header = retype(brw_vec8_grf(0, 0),
BRW_REGISTER_TYPE_UW);
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_qtr_control(brw, insn) != BRW_COMPRESSION_NONE) {
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
src_header = vec16(src_header);
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_pred_control(brw, insn) == BRW_PREDICATE_NONE);
if (brw->gen < 6)
brw_inst_set_base_mrf(brw, insn, mrf.nr);
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
/* Until gen6, writes followed by reads from the same location
* are not guaranteed to be ordered unless write_commit is set.
* If set, then a no-op write is issued to the destination
* register to set a dependency, and a read from the destination
* can be used to ensure the ordering.
*
* For gen6, only writes between different threads need ordering
* protection. Our use of DP writes is all about register
* spilling within a thread.
*/
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6) {
i956: Set the execution size correctly for scratch space writes. Otherwise, the second half isn't written, and we end up reading back black. Fixes the remaining junk drawn in glsl-max-varyings, and will likely help with a number of large real-world shaders.
2010-07-21 15:54:53 -07:00
dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
send_commit_msg = 0;
} else {
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
dest = src_header;
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
send_commit_msg = 1;
}
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6) {
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, mrf);
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
} else {
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_null_reg());
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
}
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6)
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
else
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE;
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_dp_write_message(p,
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
insn,
i965: new and updated comments
2009-03-31 10:49:41 -06:00
255, /* binding table index (255=stateless) */
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
msg_control,
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
msg_type,
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
mlen,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
true, /* header_present */
i965: Rename pixel_scoreboard_clear to last_render_target for clarity. Finding this bit in the documentation proved challenging. It wasn't in the SEND instruction's message descriptor section, nor the data port message descriptor section. It turns out to be part of the Render Target Write message's control bits, and in the documentation is named "Last Render Target Select". Shaders that use Multiple Render Targets should set this bit on the last RT write, but not on any prior ones. The GPU does update the Pixel Scoreboard appropriately, but doesn't document this bit as directly causing a scoreboard clear. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-07 22:26:40 -07:00
0, /* not a render target */
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
send_commit_msg, /* response_length */
0, /* eot */
send_commit_msg);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
}
i965: new and updated comments
2009-03-31 10:49:41 -06:00
/**
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
* Read a block of owords (half a GRF each) from the scratch buffer
* using a constant index per channel.
*
* Offset must be aligned to oword size (16 bytes). Used for register
* spilling.
i965: new and updated comments
2009-03-31 10:49:41 -06:00
*/
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
void
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
brw_oword_block_read_scratch(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
int num_regs,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned offset)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
uint32_t msg_control;
int rlen;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6)
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
offset /= 16;
i965: Don't emit register spill offsets directly into g0. g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21 14:40:49 -07:00
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
dest = retype(dest, BRW_REGISTER_TYPE_UW);
if (num_regs == 1) {
msg_control = BRW_DATAPORT_OWORD_BLOCK_2_OWORDS;
rlen = 1;
} else {
msg_control = BRW_DATAPORT_OWORD_BLOCK_4_OWORDS;
rlen = 2;
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 16:57:02 -07:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Don't emit register spill offsets directly into g0. g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21 14:40:49 -07:00
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
i965: new and updated comments
2009-03-31 10:49:41 -06:00
/* set message header global offset field (reg 0, element 2) */
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
brw_MOV(p,
i965: Don't emit register spill offsets directly into g0. g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21 14:40:49 -07:00
retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
mrf.nr,
2), BRW_REGISTER_TYPE_UD),
brw_imm_ud(offset));
i965: fix fetching constants from constant buffer in glsl path the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
2009-06-26 20:38:07 +02:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
brw_pop_insn_state(p);
}
{
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_pred_control(brw, insn) == 0);
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest); /* UW? */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6) {
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, mrf);
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
} else {
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_null_reg());
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_base_mrf(brw, insn, mrf.nr);
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
}
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_dp_read_message(p,
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
insn,
i965: new and updated comments
2009-03-31 10:49:41 -06:00
255, /* binding table index (255=stateless) */
i965: Add support for register spilling. It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19 09:25:51 -07:00
msg_control,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */
i965/fs: Add gen6 register spilling support. Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
2011-04-14 19:36:28 -07:00
BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
1, /* msg_length */
i965: Add a header_present flag for setting up dp read messages. As of gen7, we can skip the header on some messages, and this can make optimization on those messages much nicer when you've got GRFs instead of MRFs as the source.
2012-11-09 11:17:48 -08:00
true, /* header_present */
i965: Drop the eot argument to read messages, which can never be set.
2010-10-26 13:46:09 -07:00
rlen);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
}
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 11:51:22 -07:00
void
gen7_block_read_scratch(struct brw_compile *p,
struct brw_reg dest,
int num_regs,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned offset)
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 11:51:22 -07:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_pred_control(brw, insn) == BRW_PREDICATE_NONE);
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 11:51:22 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UW));
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 11:51:22 -07:00
/* The HW requires that the header is present; this is to get the g0.5
* scratch offset.
*/
brw_set_src0(p, insn, brw_vec8_grf(0, 0));
/* According to the docs, offset is "A 12-bit HWord offset into the memory
* Immediate Memory buffer as specified by binding table 0xFF." An HWORD
* is 32 bytes, which happens to be the size of a register.
*/
offset /= REG_SIZE;
assert(offset < (1 << 12));
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
gen7_set_dp_scratch_message(p, insn,
false, /* scratch read */
false, /* OWords */
false, /* invalidate after read */
num_regs,
offset,
1, /* mlen: just g0 */
num_regs, /* rlen */
true); /* header present */
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 11:51:22 -07:00
}
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
/**
* Read a float[4] vector from the data port Data Cache (const buffer).
i965: checkpoint commit: VS constant buffers Hook up a constant buffer, binding table, etc for the VS unit. This will allow using large constant buffers with vertex shaders. The new code is disabled at this time (use_const_buffer=FALSE).
2009-04-14 11:08:42 -06:00
* Location (in buffer) should be a multiple of 16.
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
* Used for fetching shader constants.
*/
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
void brw_oword_block_read(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
uint32_t offset,
uint32_t bind_table_index)
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Add support for constant buffer loads on gen6. Fixes glsl-fs-uniform-array-5.
2010-10-26 13:17:54 -07:00
/* On newer hardware, offset is in units of owords. */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6)
i965: Add support for constant buffer loads on gen6. Fixes glsl-fs-uniform-array-5.
2010-10-26 13:17:54 -07:00
offset /= 16;
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 16:57:02 -07:00
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
/* set message header global offset field (reg 0, element 2) */
brw_MOV(p,
retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
mrf.nr,
2), BRW_REGISTER_TYPE_UD),
brw_imm_ud(offset));
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
/* cast dest to a uword[8] vector */
dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6) {
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, mrf);
i965: Add support for constant buffer loads on gen6. Fixes glsl-fs-uniform-array-5.
2010-10-26 13:17:54 -07:00
} else {
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, brw_null_reg());
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_base_mrf(brw, insn, mrf.nr);
i965: Add support for constant buffer loads on gen6. Fixes glsl-fs-uniform-array-5.
2010-10-26 13:17:54 -07:00
}
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_dp_read_message(p,
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
insn,
bind_table_index,
BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW,
BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ,
i965: Use BRW_DATAPORT_READ_TARGET_DATA_CACHE instead of 0. Using the #define'd constant is better than 0 with a comment. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Chad Versace <chad.versace@intel.com>
2011-05-13 09:04:09 -07:00
BRW_DATAPORT_READ_TARGET_DATA_CACHE,
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
1, /* msg_length */
i965: Add a header_present flag for setting up dp read messages. As of gen7, we can skip the header on some messages, and this can make optimization on those messages much nicer when you've got GRFs instead of MRFs as the source.
2012-11-09 11:17:48 -08:00
true, /* header_present */
i965: Drop the eot argument to read messages, which can never be set.
2010-10-26 13:46:09 -07:00
1); /* response_length (1 reg, 2 owords!) */
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
brw_pop_insn_state(p);
i965: added new brw_dp_READ_4() function Used to read float[4] vectors from the constant buffer/surface.
2009-03-31 10:50:55 -06:00
}
i965: Add support for pull constants to the new FS backend. Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22 12:57:00 -07:00
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
void brw_fb_WRITE(struct brw_compile *p,
i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.
2010-08-20 15:32:17 -07:00
int dispatch_width,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_reg_nr,
i965: minor clean-ups
2009-02-12 15:40:04 -07:00
struct brw_reg src0,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_control,
unsigned binding_table_index,
unsigned msg_length,
unsigned response_length,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
bool eot,
bool header_present)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_type;
i965: Move the destination reg setup for 8/16 wide to the emit code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-03-14 10:51:19 -07:00
struct brw_reg dest;
if (dispatch_width == 16)
dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
else
dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6) {
i965: Use SENDC on the first render target write on gen6. This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color.
2010-10-26 09:35:34 -07:00
insn = next_insn(p, BRW_OPCODE_SENDC);
} else {
insn = next_insn(p, BRW_OPCODE_SEND);
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen >= 6) {
i965: Fix inconsistent indentation in brw_eu_emit.c. Most of these functions used three spaces for the first level of indentation, but four spaces for the next level. One used tabs and then three spaces. Some used 3/4 in a then block but 3/3 in the else block. Normally I try to avoid field days like this, but since the functions were so inconsistent, even internally, it was making it difficult to edit without introducing spurious whitespace changes. So, just get it over with. git diff -b shows 0 lines changed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-07 11:59:06 -07:00
/* headerless version, just submit color payload */
src0 = brw_message_reg(msg_reg_nr);
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
i965: Fix inconsistent indentation in brw_eu_emit.c. Most of these functions used three spaces for the first level of indentation, but four spaces for the next level. One used tabs and then three spaces. Some used 3/4 in a then block but 3/3 in the else block. Normally I try to avoid field days like this, but since the functions were so inconsistent, even internally, it was making it difficult to edit without introducing spurious whitespace changes. So, just get it over with. git diff -b shows 0 lines changed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2011-10-07 11:59:06 -07:00
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.
2010-08-20 15:32:17 -07:00
msg_type = BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
}
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src0);
brw_set_dp_write_message(p,
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
insn,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
binding_table_index,
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
msg_control,
msg_type,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
msg_length,
i965: Add support for gen6 FB writes to the new FS. This uses message headers for now, since we'll need it for MRT. We can cut out the header later.
2010-10-04 15:07:17 -07:00
header_present,
i965: Only set Last Render Target Select on the last FB write. Fixes GPU hangs in OilRush, Trine, and Amnesia: The Dark Descent, which all use MRT (multiple render targets). NOTE: This is a candidate for release branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38720 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40059 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45216 Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-02-18 21:29:29 -08:00
eot, /* last render target write */
i965: Add support for FB writes on Sandybridge.
2010-08-20 15:02:19 -07:00
response_length,
i965: Set the send commit bit on register spills as required pre-gen6. Otherwise, the subsequent read may not get the written value.
2010-07-21 13:07:12 -07:00
eot,
0 /* send_commit_msg */);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
i965: comments for brw_SAMPLE()
2009-03-24 18:05:53 -06:00
/**
* Texture sample instruction.
* Note: the msg_type plus msg_length values determine exactly what kind
* of sampling operation is performed. See volume 4, page 161 of docs.
*/
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
void brw_SAMPLE(struct brw_compile *p,
struct brw_reg dest,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_reg_nr,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
struct brw_reg src0,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned binding_table_index,
unsigned sampler,
unsigned msg_type,
unsigned response_length,
unsigned msg_length,
unsigned header_present,
unsigned simd_mode,
unsigned return_format)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Fix sampler on sandybridge Sandybridge has not much change on texture sampler with Ironlake.
2010-09-17 14:17:06 +08:00
i965/fs: Convert gen7 to using GRFs for texture messages. Looking at Lightsmark's shaders, the way we used MRFs (or in gen7's case, GRFs) was bad in a couple of ways. One was that it prevented compute-to-MRF for the common case of a texcoord that gets used exactly once, but where the texcoord setup all gets emitted before the texture calls (such as when it's a bare fragment shader input, which gets interpolated before processing main()). Another was that it introduced a bunch of dependencies that constrained scheduling, and forced waits for texture operations to be done before they are required. For example, we can now move the compute-to-MRF interpolation for the second texture send down after the first send. The downside is that this generally prevents remove_duplicate_mrf_writes() from doing anything, whereas previously it avoided work for the case of sampling from the same texcoord twice. However, I suspect that most of the win that originally justified that code was in avoiding the WAR stall on the first send, which this patch also avoids, rather than the small cost of the extra instruction. We see instruction count regressions in shaders in unigine, yofrankie, savage2, hon, and gstreamer. Improves GLB2.7 performance by 0.633628% +/- 0.491809% (n=121/125, avg of ~66fps, outliers below 61 dropped). Improves openarena performance by 1.01092% +/- 0.66897% (n=425). No significant difference on Lightsmark (n=44). v2: Squash in the fix for register unspilling for send-from-GRF, fixing a segfault in lightsmark. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Matt Turner <mattst88@gmail.com>
2013-10-09 17:17:59 -07:00
if (msg_reg_nr != -1)
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Remove writemask support from brw_SAMPLE(). The code was rather broken for non-XYZW on 8-wide, but all of our callers were using XYZW anyway. For my experiments with using writemask on texturing, I've been using manual header setup in the compiler backends, since we want to actually know what registers are written for optimization and register allocation. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-05 16:21:07 -08:00
insn = next_insn(p, BRW_OPCODE_SEND);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_pred_control(brw, insn, BRW_PREDICATE_NONE); /* XXX */
i965: make BRW_COMPRESSION_2NDHALF valid for brw_SAMPLE SIMD8 sampler messages are allowed in SIMD16 mode, and they could not work without BRW_COMPRESSION_2NDHALF. Later PRMs (gen5 and later) do not explicitly state whether BRW_COMPRESSION_2NDHALF is allowed, but they do have examples using send with SecHalf. It should be safe to assume SecHalf is valid. Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-27 15:23:56 +08:00
/* From the 965 PRM (volume 4, part 1, section 14.2.41):
*
* "Instruction compression is not allowed for this instruction (that
* is, send). The hardware behavior is undefined if this instruction is
* set as compressed. However, compress control can be set to "SecHalf"
* to affect the EMask generation."
*
* No similar wording is found in later PRMs, but there are examples
* utilizing send with SecHalf. More importantly, SIMD8 sampler messages
* are allowed in SIMD16 mode and they could not work without SecHalf. For
* these reasons, we allow BRW_COMPRESSION_2NDHALF here.
*/
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_qtr_control(brw, insn) != BRW_COMPRESSION_2NDHALF)
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
i965: make BRW_COMPRESSION_2NDHALF valid for brw_SAMPLE SIMD8 sampler messages are allowed in SIMD16 mode, and they could not work without BRW_COMPRESSION_2NDHALF. Later PRMs (gen5 and later) do not explicitly state whether BRW_COMPRESSION_2NDHALF is allowed, but they do have examples using send with SecHalf. It should be safe to assume SecHalf is valid. Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-27 15:23:56 +08:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Remove writemask support from brw_SAMPLE(). The code was rather broken for non-XYZW on 8-wide, but all of our callers were using XYZW anyway. For my experiments with using writemask on texturing, I've been using manual header setup in the compiler backends, since we want to actually know what registers are written for optimization and register allocation. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-02-05 16:21:07 -08:00
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
brw_set_sampler_message(p, insn,
binding_table_index,
sampler,
msg_type,
response_length,
msg_length,
header_present,
simd_mode,
return_format);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
}
/* All these variables are pretty confusing - we might be better off
* using bitmasks and macros for this, in the old style. Or perhaps
* just having the caller instantiate the fields in dword3 itself.
*/
void brw_urb_WRITE(struct brw_compile *p,
struct brw_reg dest,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_reg_nr,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
struct brw_reg src0,
i965: Allow C++ type safety in the use of enum brw_urb_write_flags. (From a suggestion by Francisco Jerez) If an enum represents a bitfield of flags, e.g.: enum E { A = 1, B = 2, C = 4, D = 8, }; then C++ normally prohibits statements like this: enum E x = A | B; because A and B are implicitly converted to ints before OR-ing them, and an int can't be stored in an enum without a type cast. C, on the other hand, allows an int to be implicitly converted to an enum without casting. In the past we've dealt with this situation by storing flag bitfields as ints. This avoids ugly casting at the expense of some type safety that C++ would normally have offered (e.g. we get no warning if we accidentally use the wrong enum type). However, we can get the best of both worlds if we override the | operator. The ugly casting is confined to the operator overload, and we still get the benefit of C++ making sure we don't use the wrong enum type. v2: Remove unnecessary comment and unnecessary use of "enum" keyword. Use static_cast. Reviewed-by: Chad Versace <chad.versace@linux.intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2013-08-23 13:19:19 -07:00
enum brw_urb_write_flags flags,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_length,
unsigned response_length,
unsigned offset,
unsigned swizzle)
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: Try to hook up the Sandybridge URB_WRITE SEND message. My units still hang when doing this if the VS is enabled.
2010-02-25 18:35:08 -08:00
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
i965: Try to hook up the Sandybridge URB_WRITE SEND message. My units still hang when doing this if the VS is enabled.
2010-02-25 18:35:08 -08:00
i965/eu: Change gen == 7 to gen >= 7 in a couple brw_eu_emit.c cases. Broadwell is going to use the brw_eu_emit.c code soon. We want to get the fake MRF handling and URB HWord channel mask handling. We don't need the CMP thread switch workaround, though. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 07:26:30 -07:00
if (brw->gen >= 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
i965: Enable channel masks in Ivybridge's URB_WRITE_HWORD header. This shouldn't be done using MRFs, but until I have a proper solution for dealing with MRFs, this allows my hack to keep working. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-26 17:24:38 -07:00
/* Enable Channel Masks in the URB_WRITE_HWORD message header */
i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables. Makes the new vertex shader backend work on Ivybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 02:15:56 -07:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 16:57:02 -07:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
Revert "i965/vec4: Use MOV, not OR, to set URB write channel mask bits." This reverts commit af13cf609f4257768ad8b80be8cec7f2e6ca8c81, which appears to cause huge performance problems on Ivybridge. I'd missed that the FFTID bits are in the low byte. The documentation doesn't indicate that the URB write message header actually wants FFTID - it just labels those bits as "Reserved." But it appears necessary. This does slightly more than revert the original change: originally, Broadwell had separate code generation, which used MOV, and this patch only changed it for Gen4-7. Now that both are unified, reverting this also makes Broadwell use OR. Which should be fine. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-14 12:22:16 -07:00
brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5),
BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
brw_imm_ud(0xff00));
i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables. Makes the new vertex shader backend work on Ivybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 02:15:56 -07:00
brw_pop_insn_state(p);
i965: Enable channel masks in Ivybridge's URB_WRITE_HWORD header. This shouldn't be done using MRFs, but until I have a proper solution for dealing with MRFs, this allows my hack to keep working. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-26 17:24:38 -07:00
}
i965: Try to hook up the Sandybridge URB_WRITE SEND message. My units still hang when doing this if the VS is enabled.
2010-02-25 18:35:08 -08:00
insn = next_insn(p, BRW_OPCODE_SEND);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: use BRW_MAX_MRF
2009-06-30 17:08:40 -06:00
assert(msg_length < BRW_MAX_MRF);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, brw_imm_d(0));
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_urb_message(p,
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
insn,
i965: Combine 4 boolean args of brw_urb_WRITE into a flags bitfield. The arguments to brw_urb_WRITE() were getting pretty unwieldy, and we have to add more flags to support geometry shaders anyhow. Also plumb these flags through brw_clip_emit_vue(), brw_set_urb_message(), and the vec4_instruction class. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-08-10 21:13:33 -07:00
flags,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
msg_length,
i965: Drop trailing whitespace from files shared with intel-gpu-tools. Performed via s/ *$//g. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:39:03 -08:00
response_length,
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
2006-08-09 19:14:05 +00:00
offset,
swizzle);
}
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
static int
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
brw_find_next_block_end(struct brw_compile *p, int start_offset)
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
{
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
int offset;
i965: Prepare the break/cont uip/jip setting for compacted instructions. The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 12:05:05 +01:00
void *store = p->store;
i965: Pass brw into next_offset(). The new brw_inst API is going to require a brw pointer in order to access fields (so it can do generation checks). Plumb it in now. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-07 21:15:59 -07:00
const struct brw_context *brw = p->brw;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
i965: Pass brw into next_offset(). The new brw_inst API is going to require a brw pointer in order to access fields (so it can do generation checks). Plumb it in now. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-07 21:15:59 -07:00
for (offset = next_offset(brw, store, start_offset);
offset < p->next_insn_offset;
offset = next_offset(brw, store, offset)) {
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = store + offset;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
switch (brw_inst_opcode(brw, insn)) {
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_ELSE:
case BRW_OPCODE_WHILE:
i965: Also consider HALTs a potential block end. The final halt of the fragment shader turns off the remaining channels, then jumps such that everything is turned back on. So, we can have our last ENDIF of the shader point at that directly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-12 12:47:50 -08:00
case BRW_OPCODE_HALT:
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
return offset;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
}
}
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
return 0;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
}
/* There is no DO instruction on gen6, so to find the end of the loop
* we have to see if the loop is jumping back before our start
* instruction.
*/
static int
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
brw_find_loop_end(struct brw_compile *p, int start_offset)
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
int offset;
i965/eu: Refactor jump distance scaling to use a helper function. Different generations of hardware measure jump distances in different units. Previously, every function that needed to set a jump target open coded this scaling, or made a hardcoded assumption (i.e. just used 2). Most functions start with the number of instructions to jump, and scale up to the hardware-specific value. So, I made the function match that. Others start with a byte offset, and divide by a constant (8) to obtain the jump distance. This is actually 16 / 2 (the jump scale for Gen5-7). v2: Make the helper a static inline defined in brw_eu.h, instead of an actual function in brw_eu_emit.c (as suggested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:00:25 -07:00
int scale = 16 / brw_jump_scale(brw);
i965: Prepare the break/cont uip/jip setting for compacted instructions. The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 12:05:05 +01:00
void *store = p->store;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
i965/eu: Make it clear that brw_find_loop_end only runs on Gen6+. It has Gen6+ knowledge baked in, and indeed is only called for Gen6+, but it wasn't immediately obvious that this was the case. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:06:43 -07:00
assert(brw->gen >= 6);
i965: Prepare the break/cont uip/jip setting for compacted instructions. The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 12:05:05 +01:00
/* Always start after the instruction (such as a WHILE) we're trying to fix
* up.
*/
i965: Pass brw into next_offset(). The new brw_inst API is going to require a brw pointer in order to access fields (so it can do generation checks). Plumb it in now. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-07 21:15:59 -07:00
for (offset = next_offset(brw, store, start_offset);
offset < p->next_insn_offset;
offset = next_offset(brw, store, offset)) {
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = store + offset;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_opcode(brw, insn) == BRW_OPCODE_WHILE) {
int jip = brw->gen == 6 ? brw_inst_gen6_jump_count(brw, insn)
: brw_inst_jip(brw, insn);
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
if (offset + jip * scale <= start_offset)
return offset;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
}
}
assert(!"not reached");
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
return start_offset;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
}
/* After program generation, go back and update the UIP and JIP of
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
* BREAK, CONT, and HALT instructions to their correct locations.
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
*/
void
brw_set_uip_jip(struct brw_compile *p)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
int offset;
i965/eu: Refactor jump distance scaling to use a helper function. Different generations of hardware measure jump distances in different units. Previously, every function that needed to set a jump target open coded this scaling, or made a hardcoded assumption (i.e. just used 2). Most functions start with the number of instructions to jump, and scale up to the hardware-specific value. So, I made the function match that. Others start with a byte offset, and divide by a constant (8) to obtain the jump distance. This is actually 16 / 2 (the jump scale for Gen5-7). v2: Make the helper a static inline defined in brw_eu.h, instead of an actual function in brw_eu_emit.c (as suggested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:00:25 -07:00
int br = brw_jump_scale(brw);
int scale = 16 / br;
i965: Prepare the break/cont uip/jip setting for compacted instructions. The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 12:05:05 +01:00
void *store = p->store;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6)
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
return;
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
for (offset = 0; offset < p->next_insn_offset;
i965: Pass brw into next_offset(). The new brw_inst API is going to require a brw pointer in order to access fields (so it can do generation checks). Plumb it in now. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-07 21:15:59 -07:00
offset = next_offset(brw, store, offset)) {
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = store + offset;
i965: Prepare the break/cont uip/jip setting for compacted instructions. The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 12:05:05 +01:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_cmpt_control(brw, insn)) {
i965: Prepare the break/cont uip/jip setting for compacted instructions. The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 12:05:05 +01:00
/* Fixups for compacted BREAK/CONTINUE not supported yet. */
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_opcode(brw, insn) != BRW_OPCODE_BREAK &&
brw_inst_opcode(brw, insn) != BRW_OPCODE_CONTINUE &&
brw_inst_opcode(brw, insn) != BRW_OPCODE_HALT);
i965: Prepare the break/cont uip/jip setting for compacted instructions. The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-02-03 12:05:05 +01:00
continue;
}
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
int block_end_offset = brw_find_next_block_end(p, offset);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
switch (brw_inst_opcode(brw, insn)) {
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
case BRW_OPCODE_BREAK:
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
assert(block_end_offset != 0);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
i965: Add support for loops on Ivybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-30 01:17:52 -07:00
/* Gen7 UIP points to WHILE; Gen6 points just after it */
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_uip(brw, insn,
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
(brw_find_loop_end(p, offset) - offset +
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
(brw->gen == 6 ? 16 : 0)) / scale);
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
break;
case BRW_OPCODE_CONTINUE:
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
assert(block_end_offset != 0);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
brw_inst_set_uip(brw, insn,
(brw_find_loop_end(p, offset) - offset) / scale);
i965: Make the CONT instruction point to the WHILE instruction. This fixes piglit test glsl-fs-loop-continue.shader_test on Ivybridge. According to the documentation, the CONT instruction's UIP field should point to the WHILE instruction on both Sandybridge and Ivybridge. The previous code made UIP point to the implicit DO instruction, which seems incorrect. I'm not sure how it could have worked on Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-30 01:30:55 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_uip(brw, insn) != 0);
assert(brw_inst_jip(brw, insn) != 0);
i965: Add break statement at end of BRW_OPCODE_CONTINUE case. Fixes missing break in switch defect reported by Coverity. Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-01-01 17:02:38 -08:00
break;
i965: Jump to the end of the next outer conditional block on ENDIFs. From the Ivybridge PRM, Volume 4, Part 3, section 6.24 (page 172): "The endif instruction is also used to hop out of nested conditionals by jumping to the end of the next outer conditional block when all channels are disabled." Also: "Pseudocode: Evaluate(WrEn); if ( WrEn == 0 ) { // all channels false Jump(IP + JIP); }" First, ENDIF re-enables any channels that were disabled because they didn't match the conditional. If any channels are active, it proceeds to the next instruction (IP + 16). However, if they're all disabled, there's no point in walking through all of the instructions that have no effect---it can jump to the next instruction that might re-enable some channels (an ELSE, ENDIF, or WHILE). Previously, we always set JIP on ENDIF instructions to 2 (which is measured in 8-byte units). This made it do Jump(IP + 16), which just meant it would go to the next instruction even if all channels were off. It turns out that walking over instructions while all the channels are disabled like this is worse than just instruction dispatch overhead: if there are texturing messages, it still costs a couple hundred cycles to not-actually-read from the texture results. This patch finds the next instruction that could re-enable channels and sets JIP accordingly. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-12-12 02:20:05 -08:00
case BRW_OPCODE_ENDIF:
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
if (block_end_offset == 0)
i965/eu: Refactor jump distance scaling to use a helper function. Different generations of hardware measure jump distances in different units. Previously, every function that needed to set a jump target open coded this scaling, or made a hardcoded assumption (i.e. just used 2). Most functions start with the number of instructions to jump, and scale up to the hardware-specific value. So, I made the function match that. Others start with a byte offset, and divide by a constant (8) to obtain the jump distance. This is actually 16 / 2 (the jump scale for Gen5-7). v2: Make the helper a static inline defined in brw_eu.h, instead of an actual function in brw_eu_emit.c (as suggested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 08:00:25 -07:00
brw_inst_set_jip(brw, insn, 1 * br);
i965: Jump to the end of the next outer conditional block on ENDIFs. From the Ivybridge PRM, Volume 4, Part 3, section 6.24 (page 172): "The endif instruction is also used to hop out of nested conditionals by jumping to the end of the next outer conditional block when all channels are disabled." Also: "Pseudocode: Evaluate(WrEn); if ( WrEn == 0 ) { // all channels false Jump(IP + JIP); }" First, ENDIF re-enables any channels that were disabled because they didn't match the conditional. If any channels are active, it proceeds to the next instruction (IP + 16). However, if they're all disabled, there's no point in walking through all of the instructions that have no effect---it can jump to the next instruction that might re-enable some channels (an ELSE, ENDIF, or WHILE). Previously, we always set JIP on ENDIF instructions to 2 (which is measured in 8-byte units). This made it do Jump(IP + 16), which just meant it would go to the next instruction even if all channels were off. It turns out that walking over instructions while all the channels are disabled like this is worse than just instruction dispatch overhead: if there are texturing messages, it still costs a couple hundred cycles to not-actually-read from the texture results. This patch finds the next instruction that could re-enable channels and sets JIP accordingly. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-12-12 02:20:05 -08:00
else
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
break;
i965: Jump to the end of the next outer conditional block on ENDIFs. From the Ivybridge PRM, Volume 4, Part 3, section 6.24 (page 172): "The endif instruction is also used to hop out of nested conditionals by jumping to the end of the next outer conditional block when all channels are disabled." Also: "Pseudocode: Evaluate(WrEn); if ( WrEn == 0 ) { // all channels false Jump(IP + JIP); }" First, ENDIF re-enables any channels that were disabled because they didn't match the conditional. If any channels are active, it proceeds to the next instruction (IP + 16). However, if they're all disabled, there's no point in walking through all of the instructions that have no effect---it can jump to the next instruction that might re-enable some channels (an ELSE, ENDIF, or WHILE). Previously, we always set JIP on ENDIF instructions to 2 (which is measured in 8-byte units). This made it do Jump(IP + 16), which just meant it would go to the next instruction even if all channels were off. It turns out that walking over instructions while all the channels are disabled like this is worse than just instruction dispatch overhead: if there are texturing messages, it still costs a couple hundred cycles to not-actually-read from the texture results. This patch finds the next instruction that could re-enable channels and sets JIP accordingly. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-12-12 02:20:05 -08:00
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
case BRW_OPCODE_HALT:
/* From the Sandy Bridge PRM (volume 4, part 2, section 8.3.19):
*
* "In case of the halt instruction not inside any conditional
* code block, the value of <JIP> and <UIP> should be the
* same. In case of the halt instruction inside conditional code
* block, the <UIP> should be the end of the program, and the
* <JIP> should be end of the most inner conditional code block."
*
* The uip will have already been set by whoever set up the
* instruction.
*/
i965: Rename next_ip() -> next_offset(). That we were comparing its return value with offsets should have been a clue. :) Make it take a void *store in preparation for making the function useful elsewhere. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-17 12:53:56 -07:00
if (block_end_offset == 0) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, brw_inst_uip(brw, insn));
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
assert(brw_inst_uip(brw, insn) != 0);
assert(brw_inst_jip(brw, insn) != 0);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 10:15:08 -08:00
break;
i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
2010-12-01 11:46:46 -08:00
}
}
}
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
void brw_ff_sync(struct brw_compile *p,
struct brw_reg dest,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_reg_nr,
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
struct brw_reg src0,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
bool allocate,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned response_length,
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
2011-10-07 12:26:50 -07:00
bool eot)
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
i965: Refactor Sandybridge implied move handling. This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
2011-03-16 14:09:17 -07:00
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
i965: ff sync message change for sandybridge
2010-09-17 14:23:48 +08:00
insn = next_insn(p, BRW_OPCODE_SEND);
i965: Add support for the instruction compression bits on gen6. Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
2010-12-03 11:49:29 -08:00
brw_set_dest(p, insn, dest);
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, brw_imm_d(0));
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 00:36:46 -07:00
if (brw->gen < 6)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
i965: Pass brw_compile pointer to brw_set_src[01]. This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-05-10 16:51:12 -07:00
brw_set_ff_sync_message(p,
i965: Remove constant or ignored-by-hw args from FF sync message setup.
2010-05-13 22:15:34 -07:00
insn,
allocate,
response_length,
eot);
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-13 10:48:43 +08:00
}
i965 gen6: Initial implementation of transform feedback. This patch adds basic transform feedback capability for Gen6 hardware. This consists of several related pieces of functionality: (1) In gen6_sol.c, we set up binding table entries for use by transform feedback. We use one binding table entry per transform feedback varying (this allows us to avoid doing pointer arithmetic in the shader, since we can set up the binding table entries with the appropriate offsets and surface pitches to place each varying at the correct address). (2) In brw_context.c, we advertise the hardware capabilities, which are as follows: MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64 MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4 MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16 OpenGL 3.0 requires these values to be at least 64, 4, and 4, respectively. The reason we advertise a larger value than required for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already set aside 64 binding table entries, so we might as well make them all available in both separate attribs and interleaved modes. (3) We set aside a single SVBI ("streamed vertex buffer index") for use by transform feedback. The hardware supports four independent SVBI's, but we only need one, since vertices are added to all transform feedback buffers at the same rate. Note: at the moment this index is reset to 0 only when the driver is initialized. It needs to be reset to 0 whenever BeginTransformFeedback() is called, and otherwise preserved. (4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader program to output transform feedback data as a side effect. (5) In gen6_gs_state.c, we configure the geometry shader stage to handle the SVBI pointer correctly. Note: ordering of vertices is not yet correct for triangle strips (alternate triangles are improperly oriented). This will be addressed in a future patch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-11-28 06:55:01 -08:00
/**
* Emit the SEND instruction necessary to generate stream output data on Gen6
* (for transform feedback).
*
* If send_commit_msg is true, this is the last piece of stream output data
* from this thread, so send the data as a committed write. According to the
* Sandy Bridge PRM (volume 2 part 1, section 4.5.1):
*
* "Prior to End of Thread with a URB_WRITE, the kernel must ensure all
* writes are complete by sending the final write as a committed write."
*/
void
brw_svb_write(struct brw_compile *p,
struct brw_reg dest,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned msg_reg_nr,
i965 gen6: Initial implementation of transform feedback. This patch adds basic transform feedback capability for Gen6 hardware. This consists of several related pieces of functionality: (1) In gen6_sol.c, we set up binding table entries for use by transform feedback. We use one binding table entry per transform feedback varying (this allows us to avoid doing pointer arithmetic in the shader, since we can set up the binding table entries with the appropriate offsets and surface pitches to place each varying at the correct address). (2) In brw_context.c, we advertise the hardware capabilities, which are as follows: MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64 MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4 MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16 OpenGL 3.0 requires these values to be at least 64, 4, and 4, respectively. The reason we advertise a larger value than required for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already set aside 64 binding table entries, so we might as well make them all available in both separate attribs and interleaved modes. (3) We set aside a single SVBI ("streamed vertex buffer index") for use by transform feedback. The hardware supports four independent SVBI's, but we only need one, since vertices are added to all transform feedback buffers at the same rate. Note: at the moment this index is reset to 0 only when the driver is initialized. It needs to be reset to 0 whenever BeginTransformFeedback() is called, and otherwise preserved. (4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader program to output transform feedback data as a side effect. (5) In gen6_gs_state.c, we configure the geometry shader stage to handle the SVBI pointer correctly. Note: ordering of vertices is not yet correct for triangle strips (alternate triangles are improperly oriented). This will be addressed in a future patch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-11-28 06:55:01 -08:00
struct brw_reg src0,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned binding_table_index,
i965 gen6: Initial implementation of transform feedback. This patch adds basic transform feedback capability for Gen6 hardware. This consists of several related pieces of functionality: (1) In gen6_sol.c, we set up binding table entries for use by transform feedback. We use one binding table entry per transform feedback varying (this allows us to avoid doing pointer arithmetic in the shader, since we can set up the binding table entries with the appropriate offsets and surface pitches to place each varying at the correct address). (2) In brw_context.c, we advertise the hardware capabilities, which are as follows: MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64 MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4 MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16 OpenGL 3.0 requires these values to be at least 64, 4, and 4, respectively. The reason we advertise a larger value than required for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already set aside 64 binding table entries, so we might as well make them all available in both separate attribs and interleaved modes. (3) We set aside a single SVBI ("streamed vertex buffer index") for use by transform feedback. The hardware supports four independent SVBI's, but we only need one, since vertices are added to all transform feedback buffers at the same rate. Note: at the moment this index is reset to 0 only when the driver is initialized. It needs to be reset to 0 whenever BeginTransformFeedback() is called, and otherwise preserved. (4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader program to output transform feedback data as a side effect. (5) In gen6_gs_state.c, we configure the geometry shader stage to handle the SVBI pointer correctly. Note: ordering of vertices is not yet correct for triangle strips (alternate triangles are improperly oriented). This will be addressed in a future patch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-11-28 06:55:01 -08:00
bool send_commit_msg)
{
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn;
i965 gen6: Initial implementation of transform feedback. This patch adds basic transform feedback capability for Gen6 hardware. This consists of several related pieces of functionality: (1) In gen6_sol.c, we set up binding table entries for use by transform feedback. We use one binding table entry per transform feedback varying (this allows us to avoid doing pointer arithmetic in the shader, since we can set up the binding table entries with the appropriate offsets and surface pitches to place each varying at the correct address). (2) In brw_context.c, we advertise the hardware capabilities, which are as follows: MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64 MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4 MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16 OpenGL 3.0 requires these values to be at least 64, 4, and 4, respectively. The reason we advertise a larger value than required for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already set aside 64 binding table entries, so we might as well make them all available in both separate attribs and interleaved modes. (3) We set aside a single SVBI ("streamed vertex buffer index") for use by transform feedback. The hardware supports four independent SVBI's, but we only need one, since vertices are added to all transform feedback buffers at the same rate. Note: at the moment this index is reset to 0 only when the driver is initialized. It needs to be reset to 0 whenever BeginTransformFeedback() is called, and otherwise preserved. (4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader program to output transform feedback data as a side effect. (5) In gen6_gs_state.c, we configure the geometry shader stage to handle the SVBI pointer correctly. Note: ordering of vertices is not yet correct for triangle strips (alternate triangles are improperly oriented). This will be addressed in a future patch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-11-28 06:55:01 -08:00
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
insn = next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, brw_imm_d(0));
brw_set_dp_write_message(p, insn,
binding_table_index,
0, /* msg_control: ignored */
GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE,
1, /* msg_length */
true, /* header_present */
0, /* last_render_target: ignored */
send_commit_msg, /* response_length */
0, /* end_of_thread */
send_commit_msg); /* send_commit_msg */
}
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 14:10:52 -08:00
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
static void
brw_set_dp_untyped_atomic_message(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned atomic_op,
unsigned bind_table_index,
unsigned msg_length,
unsigned response_length,
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
bool header_present)
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
unsigned msg_control =
atomic_op | /* Atomic Operation Type: BRW_AOP_* */
(response_length ? 1 << 5 : 0); /* Return data expected */
i965/eu: Use Haswell atomic messages on Broadwell. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-07-11 15:48:14 -07:00
if (brw->gen >= 8 || brw->is_haswell) {
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
msg_length, response_length,
header_present, false);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_access_mode(brw, insn) == BRW_ALIGN_1) {
if (brw_inst_exec_size(brw, insn) != BRW_EXECUTE_16)
msg_control |= 1 << 4; /* SIMD8 mode */
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dp_msg_type(brw, insn,
HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP);
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
} else {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dp_msg_type(brw, insn,
HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2);
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
}
} else {
brw_set_message_descriptor(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
msg_length, response_length,
header_present, false);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dp_msg_type(brw, insn, GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP);
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
if (brw_inst_exec_size(brw, insn) != BRW_EXECUTE_16)
msg_control |= 1 << 4; /* SIMD8 mode */
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_binding_table_index(brw, insn, bind_table_index);
brw_inst_set_dp_msg_control(brw, insn, msg_control);
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
}
void
brw_untyped_atomic(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned atomic_op,
unsigned bind_table_index,
unsigned msg_length,
unsigned response_length) {
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD));
brw_set_src1(p, insn, brw_imm_d(0));
brw_set_dp_untyped_atomic_message(
p, insn, atomic_op, bind_table_index, msg_length, response_length,
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_access_mode(brw, insn) == BRW_ALIGN_1);
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 14:01:50 -07:00
}
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
static void
brw_set_dp_untyped_surface_read_message(struct brw_compile *p,
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned bind_table_index,
unsigned msg_length,
unsigned response_length,
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
bool header_present)
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
const unsigned dispatch_width =
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
(brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16 ? 16 : 8);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
const unsigned num_channels = response_length / (dispatch_width / 8);
i965/eu: Use Haswell atomic messages on Broadwell. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-07-11 15:48:14 -07:00
if (brw->gen >= 8 || brw->is_haswell) {
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
msg_length, response_length,
header_present, false);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dp_msg_type(brw, insn,
HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
} else {
brw_set_message_descriptor(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
msg_length, response_length,
header_present, false);
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_dp_msg_type(brw, insn,
GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
/* Set mask of 32-bit channels to drop. */
unsigned msg_control = (0xf & (0xf << num_channels));
if (brw_inst_access_mode(brw, insn) == BRW_ALIGN_1) {
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
if (dispatch_width == 16)
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
msg_control |= 1 << 4; /* SIMD16 mode */
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
else
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
msg_control |= 2 << 4; /* SIMD8 mode */
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
}
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_set_binding_table_index(brw, insn, bind_table_index);
brw_inst_set_dp_msg_control(brw, insn, msg_control);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
}
void
brw_untyped_surface_read(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
i965: Don't use GL types in files shared with intel-gpu-tools. sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' \ brw_eu* brw_disasm.c brw_structs.h Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-25 15:51:24 -08:00
unsigned bind_table_index,
unsigned msg_length,
unsigned response_length)
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
{
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
const struct brw_context *brw = p->brw;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD));
brw_set_dp_untyped_surface_read_message(
p, insn, bind_table_index, msg_length, response_length,
i965: Convert brw_eu_emit.c to the new brw_inst API. v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-04 17:08:57 -07:00
brw_inst_access_mode(brw, insn) == BRW_ALIGN_1);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 14:03:13 -07:00
}
i965: add low-level support for send to pixel interpolator Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-17 21:47:22 +13:00
void
brw_pixel_interpolator_query(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg mrf,
bool noperspective,
unsigned mode,
unsigned data,
unsigned msg_length,
unsigned response_length)
{
const struct brw_context *brw = p->brw;
struct brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, mrf);
brw_set_message_descriptor(p, insn, GEN7_SFID_PIXEL_INTERPOLATOR,
msg_length, response_length,
false /* header is never present for PI */,
false);
brw_inst_set_pi_simd_mode(
brw, insn, brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16);
brw_inst_set_pi_slot_group(brw, insn, 0); /* zero unless 32/64px dispatch */
brw_inst_set_pi_nopersp(brw, insn, noperspective);
brw_inst_set_pi_message_type(brw, insn, mode);
brw_inst_set_pi_message_data(brw, insn, data);
}
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 14:10:52 -08:00
/**
* This instruction is generated as a single-channel align1 instruction by
* both the VS and FS stages when using INTEL_DEBUG=shader_time.
*
* We can't use the typed atomic op in the FS because that has the execution
* mask ANDed with the pixel mask, but we just want to write the one dword for
* all the pixels.
*
* We don't use the SIMD4x2 atomic ops in the VS because want to just write
* one u32. So we use the same untyped atomic write message as the pixel
* shader.
*
* The untyped atomic operation requires a BUFFER surface type with RAW
* format, and is only accessible through the legacy DATA_CACHE dataport
* messages.
*/
void brw_shader_time_add(struct brw_compile *p,
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 15:28:11 -07:00
struct brw_reg payload,
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 14:10:52 -08:00
uint32_t surf_index)
{
i965: Silence warning about unused brw in release builds. Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-14 22:52:35 -07:00
assert(p->brw->gen >= 7);
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 14:10:52 -08:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 16:57:02 -07:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 14:29:25 -07:00
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 14:10:52 -08:00
brw_pop_insn_state(p);
/* We use brw_vec1_reg and unmasked because we want to increment the given
* offset only once.
*/
brw_set_dest(p, send, brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_NULL, 0));
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 15:28:11 -07:00
brw_set_src0(p, send, brw_vec1_reg(payload.file,
payload.nr, 0));
i965: Simplify the shader time code by using atomic counter helpers. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-20 14:05:24 -07:00
brw_set_dp_untyped_atomic_message(p, send, BRW_AOP_ADD, surf_index,
2 /* message length */,
0 /* response length */,
false /* header present */);
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 14:10:52 -08:00
}
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