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i965: Fix writemask != 0 assertions on Sandybridge.

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This fixes myriads of regressions since commit 169f9c030c
("i965: Add an assertion that writemask != NULL for non-ARFs.").

On Sandybridge, our control flow handling (such as brw_IF) does:

   brw_set_dest(p, insn, brw_imm_w(0));
   insn->bits1.branch_gen6.jump_count = 0;

This results in a IMM destination with zero for the writemask.  IMM
destinations are rather bizarre, but the code has been working for ages,
so I'm loathe to change it.

Fixes glxgears on Sandybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2013-09-17 11:54:05 -07:00
parent d2d90d66d8
commit 34b11334d4
1 changed files with 4 additions and 2 deletions
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6
src/mesa/drivers/dri/i965/brw_eu_emit.c
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@ -126,8 +126,10 @@ brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
else {
insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
assert(dest.dw1.bits.writemask != 0 ||
dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
if (dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_MESSAGE_REGISTER_FILE) {
assert(dest.dw1.bits.writemask != 0);
}
/* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
* Although Dst.HorzStride is a don't care for Align16, HW needs
* this to be programmed as "01".