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i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.

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Makes the new vertex shader backend work on Ivybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2011-08-18 02:15:56 -07:00
parent e98ee06776
commit f7d2dcae3b
1 changed files with 3 additions and 0 deletions
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src/mesa/drivers/dri/i965/brw_eu_emit.c
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@ -2244,10 +2244,13 @@ void brw_urb_WRITE(struct brw_compile *p,
if (intel->gen == 7) {
/* Enable Channel Masks in the URB_WRITE_HWORD message header */
brw_push_insn_state(p);
brw_set_access_mode(p, BRW_ALIGN_1);
brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5),
BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
brw_imm_ud(0xff00));
brw_pop_insn_state(p);
}
insn = next_insn(p, BRW_OPCODE_SEND);