The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures. This also means that XFree86 4.2.0 support for i810 DRM
is lost.
As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM. There is a 1:1 mapping, so this
should be a noop. This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction.
Introduce tile members for future tiled buffer support.
Allow user-space to explicitly define a fence-class.
Remove the implicit fence-class mechanism.
64-bit wide buffer object flag member.
These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory. So, we have the X Server allocate that memory and tell
us the address, instead.
Remove anything dealing with the unused 'HWZ' ring buffer, do round robing of
available BPLs internally and rename static_state_offset to static_state_start.
In the alloc sub-ioctl, use the cliprects to calculate the binning rectangles
and per-bin cliprects. Then in the render sub-ioctl repeat each bin batchbuffer
for each bin cliprect.
* Fix stupid error in BPL initialization. The HWB no longer hangs, and we can
see bin batchbuffers fully initialized by it. No actual rendering occurs
though.
* Set physical address space for LOAD_INDIRECT of static indirect state.
* Free and re-allocate BPLs when necessary.
* Use TTM buffer object in the virtual address BPL path.
* Some more debugging output.
Also initialize invariant state at the beginning of the rendering stream, and
start an alternative code path for using GTT relative BPL addresses (currently
always hangs the HWB during the first frame).
* Feed the HWB synchronously, and print out any batchbuffer commands it
generates.
* Put the rendering commands into the normal ring buffer.
* Emit static state in the rendering stream, the HWB doesn't support it.
Various other minor changes.
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.
Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.
Call i915_do_cleanup_pageflip() unconditionally in preclose.
