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i915: Flesh out HWZ render sub-ioctl.

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This commit is contained in:
Michel Dänzer 2007-04-10 12:42:50 +02:00
parent d0332ff450
commit f9c3905e75
3 changed files with 42 additions and 8 deletions
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45
shared-core/i915_dma.c
View file

@ -1028,18 +1028,47 @@ static int i915_bin_init(drm_device_t *dev, int i)
static int i915_hwz_render(drm_device_t *dev, struct drm_i915_hwz_render *render)
{
drm_i915_private_t *dev_priv = dev->dev_private;
int i;
int ret, i;
unsigned int hwz_outring;
RING_LOCALS;
for (i = 0; i < dev_priv->num_bpls; i++) {
int ret = i915_bin_init(dev, i);
ret = i915_bin_init(dev, render->bpl_num);
if (ret) {
DRM_ERROR("Failed to initialize BPL %d\n", i);
return ret;
}
if (ret) {
DRM_ERROR("Failed to initialize BPL %d\n", render->bpl_num);
return ret;
}
return 0;
/* Prepare the Scene Render List */
BEGIN_RING(&dev_priv->hwz_ring, 2 * dev_priv->num_bins);
for (i = 0; i < dev_priv->num_bins; i++) {
OUT_RING(MI_BATCH_BUFFER_START);
OUT_RING(dev_priv->bins[render->bpl_num][i]->busaddr);
}
hwz_outring = outring;
/* Write the HWB command stream */
BEGIN_RING(&dev_priv->hwb_ring, 12);
OUT_RING(CMD_MI_LOAD_REGISTER_IMM);
OUT_RING(BINCTL);
OUT_RING(dev_priv->bpl[render->bpl_num]->busaddr);
OUT_RING(CMD_MI_LOAD_REGISTER_IMM);
OUT_RING(BINSCENE);
OUT_RING(((dev_priv->bin_y2 - dev_priv->bin_y1 + BIN_HEIGHT - 1) /
BIN_HEIGHT - 1) << 16 |
((dev_priv->bin_x2 - dev_priv->bin_x1 + BIN_WIDTH - 1) /
BIN_WIDTH - 1) << 10);
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
OUT_RING(render->batch_start | MI_BATCH_NON_SECURE);
OUT_RING(CMD_MI_FLUSH | MI_END_SCENE);
OUT_RING(CMD_MI_LOAD_REGISTER_IMM);
OUT_RING(HP_RING + RING_TAIL);
OUT_RING(hwz_outring);
ADVANCE_RING();
return ret;
}
static int i915_hwz_init(drm_device_t *dev, struct drm_i915_hwz_init *init)

2
shared-core/i915_drm.h
View file

@ -343,6 +343,8 @@ typedef struct drm_i915_hwz {
unsigned short y2;
} alloc;
struct drm_i915_hwz_render {
unsigned int bpl_num;
unsigned int batch_start;
} render;
};
} drm_i915_hwz_t;

3
shared-core/i915_drv.h
View file

@ -266,6 +266,9 @@ extern int i915_wait_ring(drm_i915_private_t *dev_priv, drm_i915_ring_buffer_t
#define MI_NO_WRITE_FLUSH (1 << 2)
#define MI_READ_FLUSH (1 << 0)
#define MI_EXE_FLUSH (1 << 1)
#define MI_END_SCENE (1 << 4)
#define CMD_MI_LOAD_REGISTER_IMM ((0x22 << 23)|0x1)
#define BB1_START_ADDR_MASK (~0x7)
#define BB1_PROTECTED (1<<0)