mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-05 12:28:03 +02:00
i915: More HWZ fixes and extended debugging output.
Also initialize invariant state at the beginning of the rendering stream, and start an alternative code path for using GTT relative BPL addresses (currently always hangs the HWB during the first frame).
This commit is contained in:
Michel Dänzer
parent
772c981460
commit
021ccee6c3
2 changed files with 133 additions and 58 deletions
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@ -811,6 +811,7 @@ static void i915_bmp_free(drm_device_t *dev)
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DRM_INFO("BMP freed\n");
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}
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#define VIRTUAL_BPL 0
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#define BPL_ALIGN (16 * 1024)
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static int i915_bpl_alloc(drm_device_t *dev, int bin_pitch, int bin_rows)
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@ -819,29 +820,55 @@ static int i915_bpl_alloc(drm_device_t *dev, int bin_pitch, int bin_rows)
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int i, bpl_size = (8 * bin_rows * bin_pitch + PAGE_SIZE - 1) &
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PAGE_MASK;
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if (bin_pitch <= 0 || bin_rows <= 0) {
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DRM_ERROR("Invalid bin pitch=%d rows=%d\n", bin_pitch, bin_rows);
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return DRM_ERR(EINVAL);
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}
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/* drm_pci_alloc can't handle alignment > size */
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if (bpl_size < BPL_ALIGN)
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bpl_size = BPL_ALIGN;
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#if VIRTUAL_BPL
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DRM_INFO("HWZ ring offset=0x%lx handle=%p\n",
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dev_priv->hwz_ring.map.offset, dev_priv->hwz_ring.map.handle);
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#endif
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for (i = 0; i < dev_priv->num_bpls; i++) {
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if (dev_priv->bpl[i])
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continue;
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#if VIRTUAL_BPL
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dev_priv->bpl[i] = drm_calloc(1, sizeof(*dev_priv->bpl),
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DRM_MEM_DRIVER);
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#else
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dev_priv->bpl[i] = drm_pci_alloc(dev, bpl_size, BPL_ALIGN,
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0xffffffff);
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#endif
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if (!dev_priv->bpl[i]) {
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DRM_ERROR("Failed to allocate BPL %d\n", i);
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return DRM_ERR(ENOMEM);
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}
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#if 0 /* Virtual BPL address */
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if (dev_priv->bpl[i]->busaddr & (0x3 << 29)) {
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#if VIRTUAL_BPL
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dev_priv->bpl[i]->busaddr = (dev_priv->hwz_ring.map.offset -
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dev->agp->agp_info.aper_base +
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i * bpl_size + BPL_ALIGN - 1) &
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~(BPL_ALIGN - 1);
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if (dev_priv->bpl[i]->busaddr & (0x7 << 29)) {
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DRM_ERROR("BPL %d bus address 0x%x high bits not 0\n",
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i, dev_priv->bpl[i]->busaddr);
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drm_pci_free(dev, dev_priv->bpl[i]);
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drm_free(dev_priv->bpl[i], sizeof(*dev_priv->bpl),
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DRM_MEM_DRIVER);
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dev_priv->bpl[i] = NULL;
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return DRM_ERR(ENOMEM);
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}
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dev_priv->bpl[i]->vaddr =
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(void*)(((unsigned long)dev_priv->hwz_ring.map.handle +
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i * bpl_size + BPL_ALIGN - 1) & ~(BPL_ALIGN - 1));
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DRM_INFO("BPL %d busaddr=0x%x vaddr=%p\n", i,
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dev_priv->bpl[i]->busaddr, dev_priv->bpl[i]->vaddr);
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#endif
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}
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@ -860,36 +887,79 @@ static void i915_bpl_free(drm_device_t *dev)
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if (!dev_priv->bpl[i])
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return;
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#if VIRTUAL_BPL
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drm_free(dev_priv->bpl[i], sizeof(*dev_priv->bpl), DRM_MEM_DRIVER);
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#else
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drm_pci_free(dev, dev_priv->bpl[i]);
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#endif
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dev_priv->bpl[i] = NULL;
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}
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}
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static int i915_hwb_idle(drm_i915_private_t *dev_priv)
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static int i915_hwb_idle(drm_i915_private_t *dev_priv, unsigned bpl_num)
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{
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int i, ret = 0;
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if (i915_wait_ring(dev_priv, &dev_priv->hwb_ring,
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dev_priv->hwb_ring.Size - 8, __FUNCTION__)) {
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DRM_INFO("Timeout waiting for HWB ring to go idle"
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", HWZ head: %x tail: %x/%x HWB head: %x tail: %x/%x\n",
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", PRB head: %x tail: %x/%x HWB head: %x tail: %x/%x\n",
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I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR,
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I915_READ(LP_RING + RING_TAIL) & HEAD_ADDR,
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dev_priv->ring.tail,
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I915_READ(HWB_RING + RING_HEAD) & HEAD_ADDR,
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I915_READ(HWB_RING + RING_TAIL) & HEAD_ADDR,
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dev_priv->hwb_ring.tail);
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DRM_INFO("ESR: 0x%x DMA_FADD_S: 0x%x IPEIR: 0x%x SCPD0: 0x%x\n",
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I915_READ(ESR), I915_READ(DMA_FADD_S), I915_READ(IPEIR),
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I915_READ(SCPD0));
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DRM_INFO("ESR: 0x%x DMA_FADD_S: 0x%x IPEIR: 0x%x SCPD0: 0x%x "
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"IIR: 0x%x\n", I915_READ(ESR), I915_READ(DMA_FADD_S),
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I915_READ(IPEIR), I915_READ(SCPD0),
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I915_READ(I915REG_INT_IDENTITY_R));
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DRM_INFO("BCPD: 0x%x BMCD: 0x%x BDCD: 0x%x BPCD: 0x%x\n"
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"BINSCENE: 0x%x BINSKPD: 0x%x HWBSKPD: 0x%x\n", I915_READ(BCPD),
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I915_READ(BMCD), I915_READ(BDCD), I915_READ(BPCD),
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I915_READ(BINSCENE), I915_READ(BINSKPD), I915_READ(HWBSKPD));
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return DRM_ERR(EBUSY);
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ret = DRM_ERR(EBUSY);
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}
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return 0;
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if (!dev_priv->preamble_inited[bpl_num])
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return ret;
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for (i = 0; i < dev_priv->num_bins; i++) {
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u32 *bin;
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int k;
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if (!dev_priv->bins[bpl_num] || !dev_priv->bins[bpl_num][i])
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continue;
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bin = dev_priv->bins[bpl_num][i]->vaddr;
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for (k = 6; k < 1024; k++) {
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if (bin[k]) {
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int j;
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DRM_INFO("BPL %d bin %d busaddr=0x%x contents:\n",
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bpl_num, i,
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dev_priv->bins[bpl_num][i]->busaddr);
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for (j = 0; j < 128; j++) {
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u32 *data = dev_priv->bins[bpl_num][i]->vaddr +
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j * 8 * 4;
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if (data[0] || data[1] || data[2] || data[3] ||
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data[4] || data[5] || data[6] || data[7])
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DRM_INFO("%p: %8x %8x %8x %8x %8x %8x %8x %8x\n",
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data, data[0], data[1], data[2], data[3],
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data[4], data[5], data[6], data[7]);
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}
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break;
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}
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}
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}
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return ret;
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}
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static void i915_bin_free(drm_device_t *dev)
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@ -897,7 +967,7 @@ static void i915_bin_free(drm_device_t *dev)
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int i, j;
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i915_hwb_idle(dev_priv);
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i915_hwb_idle(dev_priv, 0);
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for (i = 0; i < 3; i++) {
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if (!dev_priv->bins[i])
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@ -958,6 +1028,7 @@ static int i915_hwz_alloc(drm_device_t *dev, struct drm_i915_hwz_alloc *alloc)
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(alloc->y1 & BIN_HMASK)) / BIN_HEIGHT + 3) & ~3;
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int bin_cols = (((alloc->x2 + BIN_WIDTH - 1) & BIN_WMASK) -
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(alloc->x1 & BIN_WMASK)) / BIN_WIDTH;
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int ret;
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if (!dev_priv->bmp) {
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DRM_DEBUG("HWZ not initialized\n");
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@ -971,14 +1042,18 @@ static int i915_hwz_alloc(drm_device_t *dev, struct drm_i915_hwz_alloc *alloc)
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dev_priv->num_bpls = alloc->num_buffers;
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if (i915_bpl_alloc(dev, alloc->pitch / BIN_WIDTH, bin_rows)) {
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ret = i915_bpl_alloc(dev, bin_cols, bin_rows);
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if (ret) {
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DRM_ERROR("Failed to allocate BPLs\n");
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return DRM_ERR(ENOMEM);
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return ret;
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}
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if (i915_bin_alloc(dev, bin_cols * bin_rows)) {
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ret = i915_bin_alloc(dev, bin_cols * bin_rows);
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if (ret) {
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DRM_ERROR("Failed to allocate bins\n");
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return DRM_ERR(ENOMEM);
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return ret;
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}
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dev_priv->bin_x1 = alloc->x1;
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@ -1018,17 +1093,23 @@ static int i915_bin_init(drm_device_t *dev, int i, u32 DR1, u32 DR4)
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for (bpl_col = 0; bpl_col < dev_priv->bin_cols; bpl_col++) {
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u32 *bpl = (u32*)dev_priv->bpl[i]->vaddr +
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2 * (bpl_row * dev_priv->bin_pitch / BIN_WIDTH +
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bpl_col);
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2 * (bpl_row * dev_priv->bin_cols / BIN_WIDTH +
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4 * bpl_col);
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int j, num_bpls = dev_priv->bin_rows - bpl_row;
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if (num_bpls > 4)
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num_bpls = 4;
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DRM_DEBUG("bpl_row=%d bpl_col=%d vaddr=%p => bpl=%p num_bpls = %d\n",
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bpl_row, bpl_col, dev_priv->bpl[i]->vaddr, bpl, num_bpls);
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for (j = 0; j < num_bpls; j++) {
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drm_dma_handle_t *bin = bins[(bpl_row + j) *
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dev_priv->bin_cols +
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bpl_col];
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unsigned idx = (bpl_row + j) *
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dev_priv->bin_cols + bpl_col;
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drm_dma_handle_t *bin = bins[idx];
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DRM_DEBUG("j=%d => idx=%u bpl=%p busaddr=0x%x\n",
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j, idx, bpl, bin->busaddr);
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*bpl++ = bin->busaddr + 20;
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*bpl++ = 1 << 2 | 1 << 0;
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@ -1090,7 +1171,7 @@ static int i915_hwz_render(drm_device_t *dev, struct drm_i915_hwz_render *render
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i915_kernel_lost_context(dev_priv, &dev_priv->hwz_ring);
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}
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if (i915_hwb_idle(dev_priv)) {
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if (i915_hwb_idle(dev_priv, render->bpl_num)) {
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return DRM_ERR(EBUSY);
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}
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@ -1102,13 +1183,15 @@ static int i915_hwz_render(drm_device_t *dev, struct drm_i915_hwz_render *render
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}
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/* Write the HWB command stream */
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I915_WRITE(BINSCENE, ((dev_priv->bin_y2 - dev_priv->bin_y1 + BIN_HEIGHT
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- 1) / BIN_HEIGHT - 1) << 16 |
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((dev_priv->bin_x2 - dev_priv->bin_x1 + BIN_WIDTH - 1) /
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BIN_WIDTH - 1) << 10 | BS_MASK);
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I915_WRITE(BINSCENE, (dev_priv->bin_rows - 1) << 16 |
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(dev_priv->bin_cols - 1) << 10 | BS_MASK);
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#if VIRTUAL_BPL
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I915_WRITE(BINSKPD, (1<<7) | (1<<(7+16)));
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#endif
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I915_WRITE(BINCTL, dev_priv->bpl[render->bpl_num]->busaddr | BC_MASK);
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BEGIN_RING(&dev_priv->hwb_ring, 8);
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BEGIN_RING(&dev_priv->hwb_ring, 16);
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OUT_RING(CMD_OP_BIN_CONTROL);
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OUT_RING(0x5 << 4 | 0x6);
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OUT_RING((dev_priv->bin_y1 & BIN_HMASK) << 16 |
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@ -1117,12 +1200,30 @@ static int i915_hwz_render(drm_device_t *dev, struct drm_i915_hwz_render *render
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(((dev_priv->bin_x2 + BIN_WIDTH - 1) & BIN_WMASK) - 1));
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OUT_RING(dev_priv->bin_y1 << 16 | dev_priv->bin_x1);
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OUT_RING((dev_priv->bin_y2 - 1) << 16 | (dev_priv->bin_x2 - 1));
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OUT_RING(GFX_OP_DRAWRECT_INFO);
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OUT_RING(render->DR1);
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OUT_RING((dev_priv->bin_y1 & BIN_HMASK) << 16 |
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(dev_priv->bin_x1 & BIN_WMASK));
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OUT_RING((((dev_priv->bin_y2 + BIN_HEIGHT - 1) & BIN_HMASK) - 1) << 16 |
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(((dev_priv->bin_x2 + BIN_WIDTH - 1) & BIN_WMASK) - 1));
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OUT_RING(render->DR4);
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OUT_RING(GFX_OP_DESTBUFFER_VARS);
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OUT_RING((0x8<<20) | (0x8<<16));
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OUT_RING(GFX_OP_RASTER_RULES | (1<<5) | (2<<3));
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OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
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OUT_RING(render->batch_start | MI_BATCH_NON_SECURE);
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ADVANCE_RING();
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/* Prepare the Scene Render List */
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if (render->static_state_size) {
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DRM_INFO("Emitting %d DWORDs of static indirect state\n",
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render->static_state_size);
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BEGIN_RING(&dev_priv->ring, 4);
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OUT_RING(GFX_OP_LOAD_INDIRECT | (1<<8) | (1<<14) | 1);
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OUT_RING((render->batch_start + render->static_state_offset) |
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@ -1157,7 +1258,7 @@ static int i915_hwz_render(drm_device_t *dev, struct drm_i915_hwz_render *render
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dev_priv->ring.tail = outring;
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dev_priv->ring.space -= outcount * 4;
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i915_hwb_idle(dev_priv);
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i915_hwb_idle(dev_priv, render->bpl_num);
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BEGIN_RING(&dev_priv->hwb_ring, 2);
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OUT_RING(CMD_MI_FLUSH | MI_END_SCENE | MI_SCENE_COUNT |
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@ -1165,35 +1266,7 @@ static int i915_hwz_render(drm_device_t *dev, struct drm_i915_hwz_render *render
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OUT_RING(0);
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ADVANCE_RING();
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if (!i915_hwb_idle(dev_priv)) {
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for (i = 0; i < dev_priv->num_bins; i++) {
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u32 *bin = dev_priv->bins[render->bpl_num][i]->vaddr;
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int k;
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for (k = 6; k < 1024; k++) {
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if (bin[k]) {
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int j;
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DRM_INFO("BPL %d bin %d busaddr=0x%x contents:\n",
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render->bpl_num, i,
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dev_priv->bins[render->bpl_num][i]->busaddr);
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for (j = 0; j < 128; j++) {
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u32 *data = dev_priv->bins[render->bpl_num][i]->vaddr +
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j * 8 * 4;
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if (data[0] || data[1] || data[2] || data[3] ||
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data[4] || data[5] || data[6] || data[7])
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DRM_INFO("%p: %8x %8x %8x %8x %8x %8x %8x %8x\n",
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data, data[0], data[1], data[2], data[3],
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data[4], data[5], data[6], data[7]);
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}
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break;
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}
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}
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}
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}
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i915_hwb_idle(dev_priv, render->bpl_num);
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I915_WRITE(LP_RING + RING_TAIL, dev_priv->ring.tail);
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@ -364,6 +364,8 @@ extern int i915_wait_ring(drm_i915_private_t *dev_priv, drm_i915_ring_buffer_t
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#define BMP_PUT 0x2440
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#define BMP_OFFSET_SHIFT 5
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#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
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#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
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#define SC_UPDATE_SCISSOR (0x1<<1)
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#define SC_ENABLE_MASK (0x1<<0)
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