mesa/src/intel
José Roberto de Souza c0f1689e11
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
anv: Fix invalid resource barrier signal stage
Simulator is crashing when receiving GPGPU + Pixel as resource barrier signal
stage, what according to spec is invalid.
So here replacing the pixel stage by color, over synchronizing it a bit but
keeping it functional.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14641
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40516>
2026-03-23 16:30:39 +00:00
..
blorp Rename more sha and sha1 names to blake3 2026-03-23 07:03:28 +00:00
ci Uprev ANGLE to 599125448d7ad53b2868a7b5d2e3e8d3bfbc1717 2026-03-18 00:19:19 +00:00
common Rename more sha and sha1 names to blake3 2026-03-23 07:03:28 +00:00
compiler Final rename of sha1 names to blake3 2026-03-23 07:03:28 +00:00
decoder intel/decoder: update warning message when buildtype=release 2026-03-09 20:01:01 +00:00
dev Rename *_sha1 names to *_blake3 2026-03-23 07:03:28 +00:00
ds intel: Include available counter descriptions in the perfetto counter spec 2026-03-06 08:47:16 +00:00
executor meson: make dep_lua a disabler 2025-11-21 21:48:57 +00:00
genxml intel/genxml: Add gen125_rt.xml to default_imports in intel_genxml.py 2026-03-04 10:08:41 -08:00
isl isl: Apply VALIGN_8 fast-clear restriction on Xe3P+ 2026-03-20 21:25:39 +00:00
mda intel/mda: Use -W for color words diff and -U for regular unified diff 2026-01-28 22:11:11 +00:00
nullhw-layer build: avoid redefining unreachable() which is standard in C23 2025-07-31 17:49:42 +00:00
perf Rename sha1_* and sha_* names to blake3_* 2026-03-23 07:03:28 +00:00
shaders intel/shaders: Build for Xe3P (GFX_VERx10 == 350) 2026-03-04 11:10:34 -08:00
tools Rename *_sha1 names to *_blake3 2026-03-23 07:03:28 +00:00
vulkan anv: Fix invalid resource barrier signal stage 2026-03-23 16:30:39 +00:00
vulkan_hasvk Rename *_sha1 names to *_blake3 2026-03-23 07:03:28 +00:00
meson.build brw: Move into a new src/intel/compiler/brw subdirectory 2025-10-09 07:01:47 +00:00