Jason Ekstrand 9c658b1fc8 intel/fs/validate: Assert SEND [extended] descriptors are uniform ... This is required by code-gen since it generates a 1-wide OR and it'll blow up if the register width > 1. It's also way better than the "your register is the wrong size" assert you get from the more generic validation check. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>		2023-02-06 09:12:18 +00:00
..
blorp	intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state	2023-02-06 09:12:18 +00:00
ci	anv: expose EXT_load_store_op_none	2023-02-01 12:53:29 +00:00
common	intel/fs: Make per-sample and coarse dispatch tri-state	2023-02-06 09:12:18 +00:00
compiler	intel/fs/validate: Assert SEND [extended] descriptors are uniform	2023-02-06 09:12:18 +00:00
dev	intel/compiler: fine-grained control of dispatch widths	2023-01-27 11:00:41 +00:00
ds	intel/ds: Fix crash when allocating more intel_ds_queues than u_vector was initialized	2023-02-01 18:31:29 +00:00
genxml	intel/genxml: set unused 3DSTATE_PS_EXTRA field as mbz	2023-01-24 10:28:15 +00:00
isl	intel/isl: Disable CCS on MTL until B0 (Wa_14017353530)	2022-12-15 11:43:00 -08:00
nullhw-layer	utils: Merge util/debug.* into util/u_debug.* and remove util/debug.*	2022-11-02 07:25:39 +00:00
perf	intel: add MTL performance metrics	2022-12-09 09:13:02 +00:00
tools	anv,hasvk: migrate align32 to the right functions from util	2023-01-06 17:22:16 +00:00
vulkan	intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state	2023-02-06 09:12:18 +00:00
vulkan_hasvk	intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state	2023-02-06 09:12:18 +00:00
meson.build	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00