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db95df3da4
allows deleting piles of moves & pressure. simd16 results: Totals: Instrs: 2759547 -> 2753358 (-0.22%); split: -0.29%, +0.06% CodeSize: 41141280 -> 41071072 (-0.17%); split: -0.23%, +0.06% Totals from 332 (12.54% of 2647) affected shaders: Instrs: 648080 -> 641891 (-0.95%); split: -1.23%, +0.28% CodeSize: 9782272 -> 9712064 (-0.72%); split: -0.97%, +0.25% simd32 is a loss because of RA being stupid. again, this is obviously the right thing to do so we're doing it. stats are just a hint. Totals: Instrs: 4683556 -> 4689193 (+0.12%); split: -0.25%, +0.37% CodeSize: 70072256 -> 70171920 (+0.14%); split: -0.23%, +0.38% Number of spill instructions: 50320 -> 50316 (-0.01%) Number of fill instructions: 51530 -> 51526 (-0.01%) Totals from 351 (13.26% of 2647) affected shaders: Instrs: 1349954 -> 1355591 (+0.42%); split: -0.86%, +1.28% CodeSize: 20484224 -> 20583888 (+0.49%); split: -0.80%, +1.29% Number of spill instructions: 21762 -> 21758 (-0.02%) Number of fill instructions: 26328 -> 26324 (-0.02%) Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41510> |
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|---|---|---|
| .. | ||
| brw | ||
| elk | ||
| jay | ||
| brw_device_sha1_gen_c.py | ||
| brw_list.h | ||
| intel_gfx_ver_enum.h | ||
| intel_nir.c | ||
| intel_nir.h | ||
| intel_nir_blockify_uniform_loads.c | ||
| intel_nir_clamp_image_1d_2d_array_sizes.c | ||
| intel_nir_clamp_per_vertex_loads.c | ||
| intel_nir_lower_non_uniform_barycentric_at_sample.c | ||
| intel_nir_lower_non_uniform_resource_intel.c | ||
| intel_nir_lower_printf.c | ||
| intel_nir_lower_shading_rate_output.c | ||
| intel_nir_lower_sparse.c | ||
| intel_nir_opt_peephole_ffma.c | ||
| intel_nir_opt_peephole_imul32x16.c | ||
| intel_nir_tcs_workarounds.c | ||
| intel_prim.h | ||
| intel_shader_enums.h | ||
| meson.build | ||