Georg Lehmann 7de352e99e nir,radv: add an option to not move 8/16bit vecs ... ACO will overestimate the register demand of the sources, so we don't want to create the vector later. Foz-DB Navi48: Totals from 240 (0.30% of 80265) affected shaders: MaxWaves: 6429 -> 6435 (+0.09%) Instrs: 3406069 -> 3406646 (+0.02%); split: -0.01%, +0.03% CodeSize: 18231596 -> 18233288 (+0.01%); split: -0.01%, +0.02% VGPRs: 14768 -> 14732 (-0.24%) Latency: 18981274 -> 18979170 (-0.01%); split: -0.02%, +0.01% InvThroughput: 4247331 -> 4246634 (-0.02%); split: -0.02%, +0.01% VClause: 85453 -> 85458 (+0.01%); split: -0.01%, +0.01% Copies: 262046 -> 261971 (-0.03%); split: -0.06%, +0.03% PreVGPRs: 10899 -> 10775 (-1.14%) VALU: 1923441 -> 1923485 (+0.00%); split: -0.01%, +0.01% SALU: 457983 -> 457982 (-0.00%) VOPD: 4980 -> 4861 (-2.39%); split: +0.48%, -2.87% Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35729>		2025-06-26 09:29:43 +00:00
..
addrlib	amd/addrlib: remove the DCC page fault workaround	2025-04-01 03:23:22 -04:00
ci	zink/ci: Add glcts and piglit job on Cezanne with RADV	2025-06-25 07:09:08 +00:00
common	ac/pm4: determine spi_shader_pgm_lo_reg when PKT3_SET_SH_REG_PAIRS is used	2025-06-26 07:06:51 +00:00
compiler	aco: consider that nir_tex_src_{coord,ddx} can be the first source	2025-06-25 17:20:02 +00:00
drm-shim	amd/drm-shim: add gfx1201	2025-03-10 11:21:36 +00:00
gmlib	amd/gmlib: remove the executable bit	2025-06-12 07:44:27 +00:00
lanczoslib	radeonsi/vpe: enhance scaling quality	2025-06-12 07:44:26 +00:00
llvm	ac/llvm: use ds_bpermute_b32 for GFX12 wave64	2025-06-14 13:59:11 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: Fix CodeQL issues Pt1	2025-05-16 11:33:08 +08:00
vulkan	nir,radv: add an option to not move 8/16bit vecs	2025-06-26 09:29:43 +00:00
meson.build	radeonsi/vpe: enhance scaling quality	2025-06-12 07:44:26 +00:00