mesa/src/intel/isl
Nanley Chery eb4a581e44 intel/isl: Fix QPitch of arrayed MCS
From RENDER_SURFACE_STATE::AuxiliarySurfaceQPitch on BDW+,

   This field must be set to an integer multiple of the Surface
   Vertical Alignment

Accomplish this by aligning the height of each MCS layer to main
surface's vertical alignment. Prevents the following test group from
failing on Xe2 when a future commit enables multi-layer fast-clears in
anv:

   dEQP-VK.api.image_clearing.*.
   clear_color_attachment.multiple_layers.
   *_clamp_input_sample_count_*

The main test I used to debug this:

   dEQP-VK.api.image_clearing.core.
   clear_color_attachment.multiple_layers.
   a8b8g8r8_unorm_pack32_64x11_clamp_input_sample_count_2

Backport-to: 25.3
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37660>
2026-01-27 18:46:47 +00:00
..
tests intel/isl: Add unit tests for ISL_AUX_STATE_COMPRESSED_HIER_DEPTH. 2026-01-27 08:52:18 +00:00
gen_format_layout.py
isl.c intel/isl: Fix QPitch of arrayed MCS 2026-01-27 18:46:47 +00:00
isl.h intel/isl/gfx12.5: Alow hierarchial depth buffer write through for multi sampled surfaces 2026-01-27 08:52:12 +00:00
isl_aux_info.c intel/isl: Teach ISL about HIZ CCS partial resolves. 2026-01-27 08:52:17 +00:00
isl_drm.c intel/isl: add INTEL_DEBUG=noccs-modifier to disable CCS modifiers 2025-11-13 09:52:27 +00:00
isl_emit_cpb.c build: avoid redefining unreachable() which is standard in C23 2025-07-31 17:49:42 +00:00
isl_emit_depth_stencil.c intel/isl/gfx12.5: Alow hierarchial depth buffer write through for multi sampled surfaces 2026-01-27 08:52:12 +00:00
isl_format.c intel: Add PIPE_FORMAT_R10G10B10X2_UNORM support 2025-12-03 11:22:38 +00:00
isl_format_layout.csv intel: Enable CCS support for Yf and Ys 2026-01-26 21:09:05 +00:00
isl_genX_helpers.h isl/blorp: handle failing 96bpp linear blit case 2025-08-13 16:09:12 +00:00
isl_genX_priv.h
isl_gfx4.c isl: Drop compile time "use separate stencil" checks. 2025-03-10 17:23:07 -07:00
isl_gfx4.h
isl_gfx6.c
isl_gfx6.h
isl_gfx7.c intel/isl: Reduce scope of Yf-disabling workaround 2026-01-26 21:09:02 +00:00
isl_gfx7.h
isl_gfx8.c
isl_gfx8.h
isl_gfx9.c intel/isl: pass struct isl_tile_info to choose_image_alignment_el() 2024-06-24 17:54:30 +00:00
isl_gfx9.h intel/isl: pass struct isl_tile_info to choose_image_alignment_el() 2024-06-24 17:54:30 +00:00
isl_gfx12.c isl: Set tiling requirements for video surfaces 2025-07-16 04:08:16 +00:00
isl_gfx12.h intel/isl: pass struct isl_tile_info to choose_image_alignment_el() 2024-06-24 17:54:30 +00:00
isl_gfx20.c isl: Set tiling requirements for video surfaces 2025-07-16 04:08:16 +00:00
isl_gfx20.h intel/isl: pass struct isl_tile_info to choose_image_alignment_el() 2024-06-24 17:54:30 +00:00
isl_priv.h intel/isl: Prefer the smallest suggested tiling 2026-01-26 21:09:04 +00:00
isl_query.c
isl_storage_image.c build: avoid redefining unreachable() which is standard in C23 2025-07-31 17:49:42 +00:00
isl_surface_state.c intel/isl: Fix QPitch of arrayed MCS 2026-01-27 18:46:47 +00:00
isl_tiled_memcpy.c treewide: Replace calling to function ALIGN with align 2025-11-12 21:58:40 +00:00
isl_tiled_memcpy_normal.c
isl_tiled_memcpy_sse41.c
meson.build intel/isl: Build for Xe3 2024-10-26 07:39:29 +00:00
README

Intel Surface Layout

Introduction
============
isl is a small library that calculates the layout of Intel GPU surfaces, queries
those layouts, and queries the properties of surface formats.


Independence from User APIs
===========================
isl's API is independent of any user-facing graphics API, such as OpenGL and
Vulkan. This independence allows isl to be used a shared component by multiple
Intel drivers.

Rather than mimic the user-facing APIs, the isl API attempts to reflect Intel
hardware: the actual memory layout of Intel GPU surfaces and how one programs
the GPU to use those surfaces. For example:

  - The tokens of `enum isl_format` (such as `ISL_FORMAT_R8G8B8A8_UNORM`)
    match those of the hardware enum `SURFACE_FORMAT` rather than the OpenGL
    or Vulkan format tokens.  And the values of `isl_format` and
    `SURFACE_FORMAT` are identical.

  - The OpenGL and Vulkan APIs contain depth and stencil formats. However the
    hardware enum `SURFACE_FORMAT` does not, and therefore neither does `enum
    isl_format`. Rather than define new pixel formats that have no hardware
    counterpart, isl records the intent to use a surface as a depth or stencil
    buffer with the usage flags `ISL_SURF_USAGE_DEPTH_BIT` and
    `ISL_SURF_USAGE_STENCIL_BIT`.

  - `struct isl_surf` distinguishes between the surface's logical dimension
    from the user API's perspective (`enum isl_surf_dim`, which may be 1D, 2D,
    or 3D) and the layout of those dimensions in memory (`enum isl_dim_layout`).


Surface Units
=============

Intro
-----
ISL takes care in its equations to correctly handle conversion among surface
units (such as pixels and compression blocks) and to carefully distinguish
between a surface's logical layout in the client API and its physical layout
in memory.

Symbol names often explicitly declare their unit with a suffix:

   - px: logical pixels
   - sa: physical surface samples
   - el: physical surface elements
   - sa_rows: rows of physical surface samples
   - el_rows: rows of physical surface elements

Logical units are independent of hardware generation and are closely related
to the user-facing API (OpenGL and Vulkan). Physical units are dependent on
hardware generation and reflect the surface's layout in memory.

Definitions
-----------
- Logical Pixels (px):

  The surface's layout from the perspective of the client API (OpenGL and
  Vulkan) is in units of logical pixels. Logical pixels are independent of the
  surface's layout in memory.

  A surface's width and height, in units of logical pixels, is not affected by
  the surface's sample count. For example, consider a VkImage created with
  VkImageCreateInfo{width=w0, height=h0, samples=s0}. The surface's width and
  height at level 0 is, in units of logical pixels, w0 and h0 regardless of
  the value of s0.

  For example, the logical array length of a 3D surface is always 1, even on
  Gfx9 where the surface's memory layout is that of an array surface
  (ISL_DIM_LAYOUT_GFX4_2D).

- Physical Surface Samples (sa):

  For a multisampled surface, this unit has the obvious meaning.
  A singlesampled surface, from ISL's perspective, is simply a multisampled
  surface whose sample count is 1.

  For example, consider a 2D single-level non-array surface with samples=4,
  width_px=64, and height_px=64 (note that the suffix 'px' indicates logical
  pixels). If the surface's multisample layout is ISL_MSAA_LAYOUT_INTERLEAVED,
  then the extent of level 0 is, in units of physical surface samples,
  width_sa=128, height_sa=128, depth_sa=1, array_length_sa=1. If
  ISL_MSAA_LAYOUT_ARRAY, then width_sa=64, height_sa=64, depth_sa=1,
  array_length_sa=4.

- Physical Surface Elements (el):

  This unit allows ISL to treat compressed and uncompressed formats
  identically in many calculations.

  If the surface's pixel format is compressed, such as ETC2, then a surface
  element is equivalent to a compression block. If uncompressed, then
  a surface element is equivalent to a surface sample. As a corollary, for
  a given surface a surface element is at least as large as a surface sample.

Errata
------
ISL acquired the term 'surface element' from the Broadwell PRM [1], which
defines it as follows:

   An element is defined as a pixel in uncompressed surface formats, and as
   a compression block in compressed surface formats. For MSFMT_DEPTH_STENCIL
   type multisampled surfaces, an element is a sample.


References
==========
[1]: Broadwell PRM >> Volume 2d: Command Reference: Structures >>
     RENDER_SURFACE_STATE Surface Vertical Alignment (p325)