fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-16 02:10:25 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

intel/isl/gfx12.5: Alow hierarchial depth buffer write through for multi sampled surfaces

Browse source 
Documentation is kinda of ambiguos but at least gfx12.5 is allowed to
do hierarchial depth buffer write through for multi sampled surfaces.

BSpec: 46965
BSpec: 56419
Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31139>
This commit is contained in:
José Roberto de Souza 2023-04-06 10:26:12 -07:00 • committed by Marge Bot
parent 5ed23c14da
commit 8fdec3d161
3 changed files with 9 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/intel/isl/isl.h
View file

@ -827,8 +827,8 @@ enum isl_aux_usage {
* CCS-compressed surface contains valid data at all times.
*
* :invariant: The surface is a color surface
* :invariant: :c:member:`isl_surf.samples` == 1 for GFX 12, GFX 20 can
* be multisampled
* :invariant: :c:member:`isl_surf.samples` == 1 for GFX 12, GFX 12.5 and
* newer can be multisampled
*/
ISL_AUX_USAGE_HIZ_CCS_WT,

9
src/intel/isl/isl_emit_depth_stencil.c
View file

@ -361,12 +361,13 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
hiz.HierarchicalDepthBufferWriteThruEnable =
info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;
#if GFX_VER == 12
#if GFX_VERx10 == 120
/* The bspec docs up to GFX 12 for this bit are fairly unclear about
* exactly what is and isn't supported with HiZ write-through. It's
* fairly clear that you can't sample from a multisampled depth buffer
* with CCS. This limitation isn't called out explicitly but the docs
* for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode say:
* with CCS on GFX12.0. This limitation isn't called out explicitly but
* the docs for the CCS_E value of
* RENDER_SURFACE_STATE::AuxiliarySurfaceMode say:
*
* "If Number of multisamples > 1, programming this value means MSAA
* compression is enabled for that surface. Auxiliary surface is MSC
@ -393,7 +394,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
*/
if (hiz.HierarchicalDepthBufferWriteThruEnable)
assert(info->depth_surf->samples == 1);
#endif /* #if GFX_VER == 12 */
#endif /* #if GFX_VERx10 == 120 */
#endif /* #if GFX_VER >= 12 */
#if GFX_VER >= 8

4
src/intel/isl/isl_surface_state.c
View file

@ -774,12 +774,12 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
* compression, this means that we can't even specify MSAA depth CCS
* in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
*
* On Xe2+, the above restriction is not mentioned in the
* On GFX12.5+, the above restriction is not mentioned in the
* RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
*
* Bspec 57023 (r58975)
*/
assert(GFX_VER >= 20 || info->surf->samples == 1);
assert(GFX_VERx10 >= 125 || info->surf->samples == 1);
/* Prior to Gfx12, the dimension must not be 3D */
if (info->aux_usage == ISL_AUX_USAGE_HIZ)