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intel/isl: Prefer the smallest suggested tiling

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When choosing between the suggested tilings, create one of each allowed
and pick the smallest one. One benefit of using the standard tilings is
that miptails can avoid space waste in mipmapped compressed textures.

From the ICL PRM, Volume 5: Memory Data Formats, "MIP Layout":

   If Tiling is enabled, then each MIP is layed out using one or more
   tiles.  If TileYf or TileYs tiling is enabled (TR_MODE != NONE), then
   some of the MIPs may actually be stored in a MIPTail which fits in a
   single 64K or 4K tile. The layout above, then only applied to MIPs
   which are not packed in the MIP Tail. Note that, depending on surface
   height the Vertical Alignment that surface can actually have the last
   few mips layed out below LOD1. Using MIP Tail (if supported)
   eliminates this possibility.

In the performance CI, this helps:

   * Hogwarts Legacy on DG2 by 0.64%
   * Satisfactory on BMG by 0.89%
   * Wukong on BMG by 0.77%

Highlights on memory saved by using Tile64 from at most 10k frames in
game traces on DG2:

   * Hogwarts. 32 instances of:
	Saved 128 4KB page(s). extent=4096x4096x1 dim=2d levels=13 fmt=BC7_UNORM
   * Assassin's Creed. 8 instances of:
        Saved 768 4KB page(s). extent=120x68x192 dim=3d levels=1 fmt=R16G16B16A16_FLOAT
   * Black Ops 3. 3 instances of:
	Saved 864 4KB page(s). extent=172x140x288 dim=3d levels=1 fmt=BC6H_UF16
   * God of War. 1 instance of:
        Saved 1920 4KB page(s). extent=320x170x192 dim=3d levels=1 fmt=R16G16B16A16_FLOAT

This patch may cause regressions on SKL-TGL because the smaller surface
may not support compression. This will be fixed in a coming patch.

v2. Don't factor in the image alignments when comparing their sizes.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14074
Reviewed-by: Rohan Garg <rohan.garg@intel.com> (v1)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38063>
This commit is contained in:
Nanley Chery 2025-10-09 13:11:47 -04:00 • committed by Marge Bot
parent 13dabd941e
commit b7c5779ede
2 changed files with 37 additions and 9 deletions
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43
src/intel/isl/isl.c
View file

@ -3532,7 +3532,7 @@ isl_surf_init_s(const struct isl_device *dev,
CHOOSE(ISL_TILING_SKL_Ys);
}
/* Choose suggested 4K tilings first, then 64K tilings:
/* Choose one of the suggested tilings:
*
* The following quotes can be found in the SKL PRMs,
* Volume 5: Memory Views, Address Tiling Function Introduction
@ -3546,15 +3546,40 @@ isl_surf_init_s(const struct isl_device *dev,
* "Tile64: 64KB tiling mode which support standard-tiling including
* Mip Tails"
*/
CHOOSE(ISL_TILING_Y0);
CHOOSE(ISL_TILING_4);
CHOOSE(ISL_TILING_SKL_Yf);
CHOOSE(ISL_TILING_ICL_Yf);
CHOOSE(ISL_TILING_SKL_Ys);
CHOOSE(ISL_TILING_ICL_Ys);
CHOOSE(ISL_TILING_64);
CHOOSE(ISL_TILING_64_XE2);
isl_tiling_flags_t suggested_tilings = ISL_TILING_Y0_BIT |
ISL_TILING_4_BIT |
ISL_TILING_SKL_Yf_BIT |
ISL_TILING_ICL_Yf_BIT |
ISL_TILING_SKL_Ys_BIT |
ISL_TILING_ICL_Ys_BIT |
ISL_TILING_64_BIT |
ISL_TILING_64_XE2_BIT;
surf->size_B = 0;
u_foreach_bit(tiling, suggested_tilings & tiling_flags) {
struct isl_surf tmp_surf = {};
info_one_tiling.tiling_flags = 1 << tiling;
if (!isl_surf_init_s_with_tiling(dev, &tmp_surf, &info_one_tiling))
continue;
if (surf->size_B == 0) {
*surf = tmp_surf;
} else if ((info->usage & ISL_SURF_USAGE_PREFER_4K_ALIGNMENT) &&
tmp_surf.alignment_B != surf->alignment_B) {
if (tmp_surf.alignment_B == 4096) {
print_info(&info_one_tiling, "Enabled preferred alignment.");
*surf = tmp_surf;
}
} else if (tmp_surf.size_B < surf->size_B) {
print_info(&info_one_tiling, "Saved %d 4KB page(s).",
(int)(surf->size_B - tmp_surf.size_B) / 4096);
*surf = tmp_surf;
}
}
if (surf->size_B != 0)
return true;
CHOOSE(ISL_TILING_X);
CHOOSE(ISL_TILING_W);

3
src/intel/isl/isl_priv.h
View file

@ -284,6 +284,9 @@ _isl_notify_failure(const struct isl_surf_init_info *surf_info,
#define notify_failure(surf_info, ...) \
(_isl_notify_failure(surf_info, __FILE__, __LINE__, __VA_ARGS__), false)
#define print_info(surf_info, ...) \
_isl_notify_failure(surf_info, __FILE__, __LINE__, __VA_ARGS__)
/* This is useful for adding the isl_prefix to genX functions */
#define isl_genX(x) CONCAT2(isl_, genX(x))