mesa/src/intel/common
Francisco Jerez 622c2498d4 intel/xehp+: Import algorithm for TBIMR tiling parameter calculation.
This implements a minimalistic algorithm that can be used to obtain an
approximate solution for the integer programming problem of finding
the optimal tile dimensions based on an estimate of the tile cache
consumption per pixel of the current graphics pipeline -- Including
the TC footprint of render targets, depth and stencil buffers and
their auxiliary surfaces.  Considering other (less local) memory
accesses performed by the pipeline (like texturing and shader storage)
would be useful (and could be considered by this algorithm with little
modification), but it would be pretty difficult to estimate the L3
cache consumption per pixel of such accesses based on static analysis
of the pipeline state alone without some sort of dynamic feedback.

The present algorithm returns a config with tile area large enough to
utilize a target fraction of the L3, which can be adjusted to obtain
greater/lower utilization of the L3 at the cost of higher/lower risk
of L3 cache thrashing respectively.  The aspect ratio of the tile
layout returned attempts to minimize the number of poorly utilized
tiles around the boundaries of the framebuffer (due to partial
coverage), since having the tile sequencer process additional tiles
comes at a cost due to the latency of the additional passes, even if
they're mostly empty.  Finally, among the solutions with satisfactory
cache footprint and tile count, the tile aspect ratio closest to 1 is
returned where possible, since tiles with very high aspect ratios can
have a negative impact on cache locality.

The algorithm is primarily intended for TBIMR, but it could be used
for PTBR as well with little modifications, since the TBIMR-specific
assumptions are few and noted in comments below.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493>
2023-10-27 14:48:29 -07:00
..
i915 intel: Pass virtual memory address space ID while creating context 2023-09-07 06:39:06 +00:00
tests intel/decoder: Make intel_spec_load_filename() have separate dir and name strings 2023-08-06 20:44:59 +00:00
xe intel: Sync xe_drm.h 2023-10-23 23:24:26 +00:00
intel_aux_map.c intel: Return a bool from intel_aux_map_add_mapping 2023-10-23 21:37:24 +00:00
intel_aux_map.h intel: Return a bool from intel_aux_map_add_mapping 2023-10-23 21:37:24 +00:00
intel_batch_decoder.c intel/decoder: implement accumulated prints 2023-09-06 20:07:01 +00:00
intel_batch_decoder_stub.c intel/anv: batch stats util 2023-09-06 20:07:01 +00:00
intel_buffer_alloc.h intel: Rename gen_{mapped, clflush, invalidate} prefix to intel_{..} 2021-04-20 20:06:34 +00:00
intel_clflushopt.c intel/clflush: Add support for clflushopt instruction 2023-09-06 01:39:53 +00:00
intel_decoder.c intel/decoder: Implement support for importing genxml 2023-09-14 11:05:16 -07:00
intel_decoder.h intel/decoder: implement accumulated prints 2023-09-06 20:07:01 +00:00
intel_defines.h intel: Rename "GEN_" prefix used in common code to "INTEL_" 2021-03-10 22:23:51 +00:00
intel_disasm.c intel/tools: add ability to dump out raw kernels data 2023-04-26 10:00:54 +00:00
intel_disasm.h intel/tools: add ability to dump out raw kernels data 2023-04-26 10:00:54 +00:00
intel_engine.c intel/common: Implement the Xe functions for intel_engine 2023-03-07 15:41:36 +00:00
intel_engine.h intel/common: Add gt_id to intel_engine_class 2023-04-17 14:43:06 +00:00
intel_gem.c intel: Pass virtual memory address space ID while creating context 2023-09-07 06:39:06 +00:00
intel_gem.h intel: Pass virtual memory address space ID while creating context 2023-09-07 06:39:06 +00:00
intel_genX_state.h intel/dev: switch defect identifiers to use lineage numbers 2023-05-30 22:13:41 +00:00
intel_guardband.h intel/guardband: Take min/max instead of total size 2022-03-16 13:13:45 -05:00
intel_l3_config.c intel/mtl: Import L3 cache configurations. 2023-10-27 14:48:28 -07:00
intel_l3_config.h intel/l3: Define helper for obtaining the size of an L3 partition in KB. 2023-10-27 14:48:28 -07:00
intel_measure.c intel/measure: track batch buffer sizes 2023-09-05 11:50:02 +00:00
intel_measure.h intel/measure: track batch buffer sizes 2023-09-05 11:50:02 +00:00
intel_mem.c intel/clflush: Add support for clflushopt instruction 2023-09-06 01:39:53 +00:00
intel_mem.h intel/clflush: Add support for clflushopt instruction 2023-09-06 01:39:53 +00:00
intel_pixel_hash.h intel/xehp: Switch to coarser cross-slice pixel hashing with table permutation. 2022-01-10 18:28:35 -08:00
intel_sample_positions.c intel: Rename "gen_" prefix used in common code to "intel_" 2021-03-10 22:23:51 +00:00
intel_sample_positions.h intel/common: clamp sample location coordinate range 2022-09-21 04:05:45 +00:00
intel_tiled_render.h intel/xehp+: Import algorithm for TBIMR tiling parameter calculation. 2023-10-27 14:48:29 -07:00
intel_urb_config.c intel: split URB space between task and mesh proportionally to entry sizes 2023-04-14 15:43:50 +00:00
intel_uuid.c intel: use a shared UUID with other drivers 2023-01-17 17:36:07 +02:00
intel_uuid.h intel: use PCI info to compute device uuid 2022-01-13 03:09:36 +00:00
meson.build intel/xehp+: Import algorithm for TBIMR tiling parameter calculation. 2023-10-27 14:48:29 -07:00
mi_builder.h iris: Set MI_MATH MOCS field 2023-08-01 19:49:44 +00:00