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a364f23a6c
Tigerlake PRM: Volume 2c: Command Reference: Registers Part 2 - Registers M through Z RCU_MODE :: Compute Engine Enable This bit indicates if Compute Engine (a.k.a Dual Context or Multi Context) is enabled or not. This bit must be treated as global control for enabling and disabling of compute engine. Hardware allocates required resources for the compute engine based on this bit. .... HW reserves 4KB of URB space... Right now no gen12 platform has Dual Context enabled in kernel side, exposing a compute engine but that can change, so here adding has_compute_engine to intel_device_info and only reserving URB space if compute engine is available. While at it also fixing the error path when pb_slabs_init() fails. Bspec: 46034 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21031> |
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| i915 | ||
| tests | ||
| intel_aux_map.c | ||
| intel_aux_map.h | ||
| intel_batch_decoder.c | ||
| intel_batch_decoder_stub.c | ||
| intel_buffer_alloc.h | ||
| intel_clflush.h | ||
| intel_decoder.c | ||
| intel_decoder.h | ||
| intel_defines.h | ||
| intel_disasm.c | ||
| intel_disasm.h | ||
| intel_engine.c | ||
| intel_engine.h | ||
| intel_gem.c | ||
| intel_gem.h | ||
| intel_genX_state.h | ||
| intel_guardband.h | ||
| intel_l3_config.c | ||
| intel_l3_config.h | ||
| intel_measure.c | ||
| intel_measure.h | ||
| intel_pixel_hash.h | ||
| intel_sample_positions.c | ||
| intel_sample_positions.h | ||
| intel_urb_config.c | ||
| intel_uuid.c | ||
| intel_uuid.h | ||
| meson.build | ||
| mi_builder.h | ||