Sviatoslav Peleshko 4bf38f5652 anv: Handle all fields in VkAccelerationStructureBuildRangeInfoKHR ... Add handling of primitiveOffset and firstVertex. Fixes: f3ddfd81 ("anv: Build BVHs on the GPU with GRL") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8296 Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21342>		2023-02-24 07:08:05 +00:00
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blorp	intel/blorp: Allocate only necessary amount of VERTEX_BUFFER_STATE	2023-02-23 14:27:30 +00:00
ci	ci/intel: Update hasvk HSW xfails	2023-02-23 16:02:14 +00:00
common	intel: Make gen12 URB space reservation dependent on compute engine presence	2023-02-23 14:27:30 +00:00
compiler	intel/compiler: remove unused field from fs_thread_payload	2023-02-23 08:04:24 +00:00
dev	intel: Add extra zeros at the end of debug identifiers	2023-02-24 04:57:40 +00:00
ds	intel/ds: track end of pipe bits	2023-02-06 09:12:18 +00:00
genxml	intel/genxml: add missing power well control bits	2023-02-08 02:56:28 +00:00
isl	isl: fix some documentation	2023-02-14 16:55:21 +00:00
nullhw-layer	vulkan/layers: Use PUBLIC instead of VK_LAYER_EXPORT	2023-02-17 03:42:34 +00:00
perf	intel/perf: also add the oa timestamp shift on MTL	2023-02-17 12:10:05 +00:00
tools	anv,hasvk: migrate align32 to the right functions from util	2023-01-06 17:22:16 +00:00
vulkan	anv: Handle all fields in VkAccelerationStructureBuildRangeInfoKHR	2023-02-24 07:08:05 +00:00
vulkan_hasvk	anv, hasvk: Align workaround address to 32B	2023-02-24 04:57:40 +00:00
meson.build	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00