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intel/ds: track end of pipe bits

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
This commit is contained in:
Lionel Landwerlin 2022-11-08 16:43:33 +02:00 • committed by Marge Bot
parent a242500eb4
commit e37f458207
5 changed files with 10 additions and 3 deletions
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3
src/intel/ds/intel_driver_ds.cc
View file

@ -387,7 +387,7 @@ custom_trace_payload_as_extra_end_stall(perfetto::protos::pbzero::GpuRenderStage
auto data = event->add_extra_data();
data->set_name("stall_reason");
snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s : %s",
snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s : %s",
(payload->flags & INTEL_DS_DEPTH_CACHE_FLUSH_BIT) ? "+depth_flush" : "",
(payload->flags & INTEL_DS_DATA_CACHE_FLUSH_BIT) ? "+dc_flush" : "",
(payload->flags & INTEL_DS_HDC_PIPELINE_FLUSH_BIT) ? "+hdc_flush" : "",
@ -403,6 +403,7 @@ custom_trace_payload_as_extra_end_stall(perfetto::protos::pbzero::GpuRenderStage
(payload->flags & INTEL_DS_HDC_PIPELINE_FLUSH_BIT) ? "+hdc_flush" : "",
(payload->flags & INTEL_DS_CS_STALL_BIT) ? "+cs_stall" : "",
(payload->flags & INTEL_DS_UNTYPED_DATAPORT_CACHE_FLUSH_BIT) ? "+udp_flush" : "",
(payload->flags & INTEL_DS_END_OF_PIPE_BIT) ? "+eop" : "",
payload->reason ? payload->reason : "unknown");
assert(strlen(buf) > 0);

1
src/intel/ds/intel_driver_ds.h
View file

@ -57,6 +57,7 @@ enum intel_ds_stall_flag {
INTEL_DS_CS_STALL_BIT = BITFIELD_BIT(12),
INTEL_DS_UNTYPED_DATAPORT_CACHE_FLUSH_BIT = BITFIELD_BIT(13),
INTEL_DS_PSS_STALL_SYNC_BIT = BITFIELD_BIT(14),
INTEL_DS_END_OF_PIPE_BIT = BITFIELD_BIT(15),
};
/* Convert internal driver PIPE_CONTROL stall bits to intel_ds_stall_flag. */

3
src/intel/ds/intel_tracepoints.py
View file

@ -177,7 +177,8 @@ def define_tracepoints(args):
['DEPTH_STALL', 'depth_stall'],
['CS_STALL', 'cs_stall'],
['UNTYPED_DATAPORT_CACHE_FLUSH', 'udp_flush'],
['PSS_STALL_SYNC', 'pss_stall']]
['PSS_STALL_SYNC', 'pss_stall'],
['END_OF_PIPE', 'eop']]
begin_end_tp('stall',
tp_args=[ArgStruct(type='uint32_t', var='flags'),

1
src/intel/vulkan/anv_utrace.c
View file

@ -324,6 +324,7 @@ anv_pipe_flush_bit_to_ds_stall_flag(enum anv_pipe_bits bits)
{ .anv = ANV_PIPE_STALL_AT_SCOREBOARD_BIT, .ds = INTEL_DS_STALL_AT_SCOREBOARD_BIT, },
{ .anv = ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, .ds = INTEL_DS_UNTYPED_DATAPORT_CACHE_FLUSH_BIT, },
{ .anv = ANV_PIPE_PSS_STALL_SYNC_BIT, .ds = INTEL_DS_PSS_STALL_SYNC_BIT, },
{ .anv = ANV_PIPE_END_OF_PIPE_SYNC_BIT, .ds = INTEL_DS_END_OF_PIPE_BIT, },
};
enum intel_ds_stall_flag ret = 0;

5
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1855,7 +1855,10 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
return;
const bool trace_flush =
(bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_STALL_BITS | ANV_PIPE_INVALIDATE_BITS)) != 0;
(bits & (ANV_PIPE_FLUSH_BITS |
ANV_PIPE_STALL_BITS |
ANV_PIPE_INVALIDATE_BITS |
ANV_PIPE_END_OF_PIPE_SYNC_BIT)) != 0;
if (trace_flush)
trace_intel_begin_stall(&cmd_buffer->trace);