mesa/src/intel
Kenneth Graunke 32cce2f397 intel/brw: Set appropriate types for 16-bit sampler trailing components
16-bit SIMD8 sampler writeback messages come with a bit of padding in
them, requiring us to emit a LOAD_PAYLOAD to reorganize the data into
the padding-free format expected by NIR.  Additionally, we may reduce
the response length on the sampler messages based on which components
of the (always vec4) NIR destination are actually in use.  When we do
that, dest_size > read_size, and the trailing components are all empty
BAD_FILE registers, indicating the contents are undefined.

Unfortunately, we can't ignore those trailing components entirely.
In the past, we left them default-initialized, giving us a BAD_FILE
register with UD type (which didn't matter, since all sampler returns
were 32-bit).  But with 16-bit, this was confusing the LOAD_PAYLOAD.
For example, writing RGB and skipping A (without sparse) would produce
read_size = 3 and dest_size = 4 and nir_dest[5] containing:

   nir_dest[] = <R:hf, G:hf, B:hf, blank-A:ud, blank-sparse:ud>

We'd then call LOAD_PAYLOAD on the first 4 sources, causing it to see
3 HF's and a UD, and try to copy the full 32-bit value at the end,
instead of 16-bits of pad like we intended.  This meant it would
overflow the destination register's size, triggering validation errors.

Thanks to Ian Romanick for noticing this, writing a test, and also
coming up with a nearly identical fix.

Fixes: 0116430d39 ("intel/brw: Handle 16-bit sampler return payloads")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11617
References: https://gitlab.freedesktop.org/mesa/crucible/-/merge_requests/152
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30529>
2024-08-06 17:26:05 +00:00
..
blorp anv: Propagate protected information to blorp_batch_isl_copy_usage() 2024-07-26 20:36:32 +00:00
ci ci: simplify setting .no-auto-retry now that it isn't bundled with unrelated rules: 2024-07-07 19:31:44 +00:00
common intel/common: Remove blank lines in intel_set_ps_dispatch_state() (xe2) 2024-07-26 21:02:24 +00:00
compiler intel/brw: Set appropriate types for 16-bit sampler trailing components 2024-08-06 17:26:05 +00:00
decoder intel/decoder: Handle HCP_PAK_INSERT_OBJECT 2024-08-02 07:15:59 +00:00
dev intel/dev: Support new topology type with SIMD16 EUs 2024-08-05 07:01:47 -07:00
ds anv/hasvk: add indirect tracepoint arguments 2024-08-03 16:03:04 +03:00
genxml intel/genxml: adds a value of reference pic to HCP_SURFACE_STATE 2024-08-02 07:15:59 +00:00
isl isl: Fix Xe2 protected mask 2024-07-26 20:36:32 +00:00
nullhw-layer build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
perf intel/dev: Support new topology type with SIMD16 EUs 2024-08-05 07:01:47 -07:00
shaders meson: use glslang --depfile argument when possible 2024-05-20 17:34:17 +00:00
tools build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
vulkan anv/measure: ignore events from reused command buffers 2024-08-05 23:45:41 +00:00
vulkan_hasvk hasvk: Conditionally expose VK_KHR_present_wait 2024-08-06 11:39:38 +08:00
meson.build build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00