Georg Lehmann ad80b554f4 spirv: use feq for OpIsInf ... This effectively reverts fcca6a83cd because feq was clarified to be ordered when used with exact and without fast math flags. It's common for HW to only have free abs for floating point instructions. Foz-DB Navi21: Totals from 63 (0.08% of 80065) affected shaders: Instrs: 337027 -> 336667 (-0.11%); split: -0.12%, +0.02% CodeSize: 1846752 -> 1845000 (-0.09%); split: -0.13%, +0.03% Latency: 3401087 -> 3400633 (-0.01%); split: -0.04%, +0.03% InvThroughput: 847299 -> 845939 (-0.16%); split: -0.19%, +0.03% VClause: 7693 -> 7694 (+0.01%) Copies: 45175 -> 45240 (+0.14%); split: -0.12%, +0.27% PreSGPRs: 3555 -> 3553 (-0.06%) PreVGPRs: 4565 -> 4564 (-0.02%) VALU: 225473 -> 225245 (-0.10%); split: -0.13%, +0.03% SALU: 44735 -> 44625 (-0.25%) Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35437>		2025-06-11 18:34:21 +00:00
..
tests	spirv: Emit code for NonSemantic.DebugPrintf if supported	2025-04-10 19:31:37 +00:00
gl_spirv.c	mesa: Use the new spirv_capabilities struct	2024-05-09 01:14:22 +00:00
GLSL.ext.AMD.h	spirv: Update headers and grammer JSON	2023-08-18 16:57:22 +00:00
GLSL.std.450.h	spirv: bump headers	2025-06-06 14:38:17 +00:00
meson.build	spirv/tests: add a test for force_ssbo_non_uniform	2025-03-05 19:56:50 +00:00
nir_spirv.h	spirv: move workarounds to an inner struct in spirv_to_nir_options	2025-03-05 19:56:50 +00:00
NonSemanticShaderDebugInfo100.h	spirv: bump headers	2025-06-06 14:38:17 +00:00
OpenCL.std.h	spirv: bump headers	2025-06-06 14:38:17 +00:00
spir-v.xml	spirv: Update headers and metadata from latest Khronos commit	2025-03-25 02:29:26 +00:00
spirv.core.grammar.json	spirv: bump headers	2025-06-06 14:38:17 +00:00
spirv.h	spirv: bump headers	2025-06-06 14:38:17 +00:00
spirv2nir.c	spirv: Get rid of the old caps struct	2024-05-09 01:14:23 +00:00
spirv_info_gen.py	spirv: Update SPIR-V grammar to use aliases	2024-10-10 02:48:00 +00:00
spirv_to_nir.c	vtn: Handle non-32b tex dests	2025-06-11 17:48:10 +00:00
vtn_alu.c	spirv: use feq for OpIsInf	2025-06-11 18:34:21 +00:00
vtn_amd.c	nir: Drop nir_dest	2023-08-14 21:22:53 +00:00
vtn_bindgen2.c	vtn_bindgen2: Fix memory corruption	2025-03-03 17:25:58 +00:00
vtn_cfg.c	vtn: (Silently) handle FunctionParameterAttributeNo{Capture,Write}	2025-05-28 01:08:20 +00:00
vtn_cmat.c	spirv: Refactor to use glsl_type to pick ALU ops	2025-04-29 16:29:37 +00:00
vtn_debug.c	vtn: Add a debug flag to dump SPIR-V assembly	2024-08-28 21:52:59 +00:00
vtn_gather_types_c.py	spirv: OpAsmTargetINTEL is untyped	2025-03-08 19:54:19 +00:00
vtn_generator_ids_h.py	util,vulkan,mesa,compiler: Generate source files with utf8 encoding from mako template	2023-12-07 12:41:07 +00:00
vtn_glsl450.c	spirv: clamp/sign-extend non 32bit ldexp exponents	2025-04-03 12:35:59 +00:00
vtn_opencl.c	vtn/opencl: support fp16 builtins	2025-06-05 13:17:27 +00:00
vtn_private.h	spirv: Refactor to use glsl_type to pick ALU ops	2025-04-29 16:29:37 +00:00
vtn_structured_cfg.c	spirv: move workarounds to an inner struct in spirv_to_nir_options	2025-03-05 19:56:50 +00:00
vtn_subgroup.c	vtn: Handle SPV_KHR_uniform_group_instructions	2025-05-28 01:08:20 +00:00
vtn_variables.c	compiler/types: add a bfloat16 type	2025-04-29 16:29:36 +00:00