Commit graph

34701 commits

Author SHA1 Message Date
Rhys Perry
ffba56cc3c nv50/ir: improve maintainability of Target*::initOpInfo()
This is mainly useful for when one needs to add new opcodes in a painless
and reliable way.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2018-06-29 16:47:27 +02:00
Rhys Perry
d885303a38 nv50/ir: fix image stores with indirect handles
Having this if statement here prevented the next if statement from being
reached in the case of image stores, which is needed for instructions with
indirect bindless handles like "STORE TEMP[ADDR[2].x+1](1) ...".

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2018-06-29 16:07:59 +02:00
Marek Olšák
5a6414f135 radeonsi: implement vertex color clamping for tess and GS 2018-06-28 22:41:12 -04:00
Marek Olšák
034b385fc2 radeonsi: move VS_STATE_SGPR before draw SGPRs
for vertex color clamping.
2018-06-28 22:27:25 -04:00
Marek Olšák
0c554bc5d5 radeonsi: don't use malloc in si_generate_gs_copy_shader 2018-06-28 22:27:25 -04:00
Marek Olšák
7bac3b589c radeonsi: disable DCC statistics gathering on everything but Stoney
I think we don't need it on other chips.
2018-06-28 22:27:25 -04:00
Marek Olšák
0da94fa19c radeonsi: don't enable DCC statistics gathering for small surfaces 2018-06-28 22:27:25 -04:00
Marek Olšák
f8b0c54e3f radeonsi: simplify logic around vi_separate_dcc_try_enable 2018-06-28 22:27:25 -04:00
Marek Olšák
41f80373b4 radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
2018-06-28 22:27:25 -04:00
Marek Olšák
fb28bf23db radeonsi: remove references to Evergreen 2018-06-28 22:27:25 -04:00
Marek Olšák
1542169a4a radeonsi: enable shader caching for compute shaders
Compute shaders were not using the shader cache.
2018-06-28 22:27:25 -04:00
Marek Olšák
d77557c9db radeonsi: store compute local_size into tgsi_shader_info
This is kinda a hack, but it's enough for the shader cache.
2018-06-28 22:27:25 -04:00
Marek Olšák
d13f240269 radeonsi: unify duplicated code for initial shader compilation 2018-06-28 22:27:25 -04:00
Marek Olšák
7d6ec9d43b radeonsi/gfx9: insert the barrier between merged shaders inside the if block 2018-06-28 22:27:25 -04:00
Joe M. Kniss
70425bcfe6 gallium: plumb invariant output attrib thru TGSI
Add support for glsl 'invariant' modifier for output data declarations.
Gallium drivers that use TGSI serialization currently loose invariant
modifiers in glsl shaders.

v2: use boolean for invariant instead of unsigned.

Tested: chromiumos on qemu with virglrenderer.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-06-29 11:11:54 +10:00
Rhys Perry
c92eb71a65 nvc0: remove magic values in nve4_set_tex_handles()
With this commit, things no longer break if NVC0_CB_AUX_TEX_INFO is
changed to anything other than 0x20.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2018-06-28 18:22:06 +02:00
Rhys Perry
6bb0f87c60 nvc0/ir: fix TargetNVC0::insnCanLoadOffset()
Previously, TargetNVC0::insnCanLoadOffset() returned whether the offset
could be set to a specific value. The IndirectPropagation pass expected
it to return whether the offset could be increased by a specific value,
which is what TargetNV50::insnCanLoadOffset() does.

Fixes: 37b67db6ae
	("nvc0/ir: be careful about propagating very large offsets into const load")

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2018-06-28 18:22:06 +02:00
Alok Hota
5b7d4f9428 swr/rast: Updating code style based on current clang-format rules
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-06-28 08:18:14 -05:00
Vinson Lee
f90a60fe79 swr/rast: Fix addPassesToEmitFile usage with llvm-7.0.
Fix build error after llvm-7.0svn r332881 ("CodeGen: Add a dwo output
file argument to addPassesToEmitFile and hook it up to dwo output.").

  CXX      rasterizer/jitter/libmesaswr_la-JitManager.lo
rasterizer/jitter/JitManager.cpp:368:93: error: too few arguments to function call, expected at least 4, have 3
        pTarget->addPassesToEmitFile(*pMPasses, filestream, TargetMachine::CGFT_AssemblyFile);
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~                                                        ^

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-06-28 08:18:06 -05:00
Alok Hota
c7e9102d89 swr/rast: Handling removed LLVM intrinsics in trunk
- Functionality replaced with emulated intrinsics
- Fixes Bug 106558

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-06-28 08:18:00 -05:00
Alok Hota
83d3ddd0ec swr/rast: Adding SCATTERPS functionality to BuilderGfxMem
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-06-28 08:17:55 -05:00
Alok Hota
4509cdbb37 swr/rast: Adding Read/Write specifier to TranslateGfxAddress stack
- Removing unused generic translate function
- Requiring read/write specifier in builder_gfx_mem

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-06-28 08:17:33 -05:00
Chad Versace
dc6665422a gallium: Fix automake for Android (v2)
Chromium OS uses Autotools and pkg-config when building Mesa for
Android. The gallium drivers were failing to find the headers and
libraries for zlib and Android's libbacktrace.

v2:
  - Don't add a check for zlib.pc. configure.ac already checks for
    zlib.pc elsewhere. [for tfiga]
  - Check for backtrace.pc separately from the other Android libs.
    [for tfiga]

Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-06-27 19:58:16 -07:00
Eric Anholt
ad1a4cb563 v3d: Fix Z clipping when viewport.scale[2] is negative.
Fixes:
dEQP-GLES3.functional.shaders.builtin_variable.depth_range_fragment
dEQP-GLES3.functional.shaders.builtin_variable.depth_range_vertex
2018-06-27 09:35:51 -07:00
Eric Anholt
9f80bcc2bc v3d: Convert a bunch of our "minus one" fields over to the new XML attr.
This fixes up their formatting for CLIF files and makes the code more
legible.
2018-06-27 09:13:48 -07:00
Dave Airlie
a6b64d6dde virgl: add ARB_texture_view support
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2018-06-27 14:08:00 +10:00
Dave Airlie
318ff60ccd radeon: duplicate cmask surface for now.
The radeon winsys isn't linked against the ac code, I have vague
memories of this causing some problems before, for now fix the build
but just duplicating the code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-06-26 11:26:35 +10:00
Marek Olšák
bd963f8430 radeonsi: rename r600_transfer -> si_transfer
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
eabeeb86b2 radeonsi: properly set cmask_buffer in si_reallocate_texture_inplace
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
d4755ef389 radeonsi: remove redundant si_texture::cmask_size
cmask_buffer and surface.cmask_size can replace its role.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
2a8d1039b6 radeonsi: inline struct r600_cmask_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
166250f4e5 radeonsi: move CMASK size computation into ac_surface
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
3da693b7d9 ac/surface: move cmask_size/alignment into radeon_surf
cmask_size is changed to uint32_t because it can't be greater than 4GB.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
2d64a68c6f radeonsi: rename r600_surface -> si_surface
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
218e133695 radeonsi: rename r600_memory_object -> si_memory_object
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
e5df04f13d radeonsi: remove unused r600_memory_object::offset
The real offset is passed through resource_from_memobj.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
45004abfd5 radeonsi: unify duplicated texture_from_handle & texture_from_memobj
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
cac7ab1192 radeonsi: reorder and initialize more fields in si_reallocate_texture_inplace
Some fields shouldn't be initialized, like framebuffers_bound and other stats.
It's hopefully complete now.

Cc: 18.1 <mesa-stable@lists.freedesktop.org>
2018-06-25 18:33:58 -04:00
Marek Olšák
7888245ef3 radeonsi: stop using lp_build_emit_llvm_unary/binary
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
0810f15046 radeonsi: stop using lp_build_alloc
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
21ba8a204e radeonsi: use gallivm less
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
965904eebd radeonsi: stop using lp_bld_intr.h
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
6ab54d25a6 radeonsi: remove last uses of lp_build_context::undef
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
30f3e2200a radeonsi: stop using lp_bld_arit.h
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
5f54fc3ad1 radeonsi: stop using lp_build_gather_values
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
7bd40dc2f2 radeonsi: clean up some #includes
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Marek Olšák
f154555733 radeonsi: clean up passing the is_monolithic flag for compilation
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-06-25 18:33:58 -04:00
Robert Foss
5a34aba07d
gallium/util: Fix build error due to cast to different size
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-06-25 18:54:09 +02:00
Gert Wollny
eebb65258d r600/sb: give the scheduler more margin to find valid instructions groups
For instruction sequences that change the address register with every load
the current limit to bail out of the scheduler and reject the optimisation
was too tight, i.e. it was expected that at least one pending instruction
would be scheduled each time.

Give the scheduler more margin to sort out these load sequences by allowing
a number of rounds where no instruction is scheduled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106163

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-06-25 05:40:19 +01:00
Gert Wollny
cd7db0ab0a r600/sb: fix rotated register in while loop
This patch is based on
https://lists.freedesktop.org/archives/mesa-dev/2018-February/185805.html

Dave Airlie:

 "A bunch of CTS tests led me to write
  tests/shaders/ssa/fs-while-loop-rotate-value.shader_test
  which r600/sb always fell over on.

  GCM seems to move some of the copies into other basic blocks,
  if we don't allow this to happen then it doesn't seem to schedule
  them badly.

  Everything I've read on SSA/phi copies say they have to happen
  in parallel, so keeping them in the same basic block seems like
  a good way to keep some of that property."

This patch differs from the one proposed by Dave in that it only adds
the NF_DONT_MOVE flag to copy_move instructions that are created by split_phi*
and that are located in loops.

Fixes piglit: tests/shaders/ssa/fs-while-loop-rotate-value.shader_test
(no regressions in the shader set). It also fixes all failing tests from

  dEQP-GLES3.functional.shaders.loops.*

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-06-25 05:39:41 +01:00