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Author SHA1 Message Date
Eric Anholt
ff0eb45f47 i965: Fix array indexing of arrays of matrices. 
The deleted code was meant to be handling indexing of a matrix, which
would have been a noop if it had been correct.
 2010-09-28 16:26:49 -07:00
Dave Airlie
301ab49605 r600g: move radeon.h members around to add back map flushing. 2010-09-29 09:19:22 +10:00
Dave Airlie
53b3933ce6 r600g: add evergreen texture border support to new path 2010-09-29 09:19:22 +10:00
Dave Airlie
23be883c9b r600g: add back evergreen name. 2010-09-29 09:19:22 +10:00
Eric Anholt
17f3b8097d i965: Don't try to emit interpolation for unused varying slots. 
Fixes:
glsl-fs-varying-array
glsl-texcoord-array
glsl-texcoord-array-2
glsl-vs-varying-array
 2010-09-28 14:53:36 -07:00
Eric Anholt
5272c6a7a2 i965: Do interpolation for varying matrices and arrays in the FS backend. 
Fixes:
glsl-array-varying-01
glsl-vs-mat-add-1
glsl-vs-mat-div-1
glsl-vs-mat-div-2
glsl-vs-mat-mul-2
glsl-vs-mat-mul-3
 2010-09-28 14:50:59 -07:00
Eric Anholt
586b4b500f glsl: Also update implicit sizes of varyings at link time. 
Otherwise, we'll often end up with gl_TexCoord being 0 length, for
example.  With ir_to_mesa, things ended up working out anyway, as long
as multiple implicitly-sized arrays weren't involved.
 2010-09-28 14:37:26 -07:00
Eric Anholt
b9a59f0358 i965: Add support for ARB_fragment_coord_conventions to the new FS backend. 
Fixes:
glsl-arb-frag-coord-conventions
glsl-fs-fragcoord
 2010-09-28 13:42:52 -07:00
Eric Anholt
701c5f11c9 i965: Add support for ir_loop counters to the new FS backend. 
Fixes:
glsl1-discard statement in for loop
glsl-fs-loop-two-counter-02
glsl-fs-loop-two-counter-04
 2010-09-28 13:31:01 -07:00
Tilman Sauerbeck
35f94b1942 r600g: Cleaned up index buffer reference handling in the draw module. 
This fixes a buffer leak.

Signed-off-by: Tilman Sauerbeck <tilman@code-monkey.de>
 2010-09-28 22:12:23 +02:00
Eric Anholt
89f6783d17 i965: Add support for MRT to the new FS backend. 
Fixes these tests using gl_FragData or just gl_FragDepth:
glsl1-Preprocessor test (extension test 1)
glsl1-Preprocessor test (extension test 2)
glsl-bug-22603
 2010-09-28 12:37:21 -07:00
Eric Anholt
86fd11262c i965: Add support for non-color render target write data to new FS backend. 
This is the first time these payload bits have made sense to me,
outside of brw_wm_pass* structure.

Fixes: glsl1-gl_FragDepth writing
 2010-09-28 12:37:21 -07:00
Vinson Lee
f46a61554f scons: Add program/sampler.cpp to SCons build. 
This is a follow-up to commit a32893221c.

Fixes MinGW SCons build.
 2010-09-28 12:03:45 -07:00
Eric Anholt
2999a44968 i965: Set up sampler numbers in the FS backend. 
+10 piglits
 2010-09-28 11:37:08 -07:00
Eric Anholt
a32893221c mesa: Pull ir_to_mesa's sampler number fetcher out to shared code. 2010-09-28 11:37:08 -07:00
Jerome Glisse
723a655ed3 r600g: avoid rebuilding the vertex shader if no change to input format 
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
 2010-09-28 14:34:25 -04:00
Jerome Glisse
fe790a3c34 r600g: suspend/resume occlusion query around clear/copy 
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
 2010-09-28 14:24:18 -04:00
Marek Olšák
11eb422a16 configure.ac: do not build xorg-r300g by default 
NOTE: This is a candidate for the 7.9 branch.
 2010-09-28 19:38:40 +02:00
Marek Olšák
a1aec2e2be configure.ac: look for libdrm_radeon before building gallium/r300,r600 
NOTE: This is a candidate for the 7.9 branch.
 2010-09-28 19:38:39 +02:00
Eric Anholt
9e96c737f8 i965: Subtract instead of adding when computing y delta in new FS backend. 
Fixes 7 piglit cases.
 2010-09-28 10:19:54 -07:00
Eric Anholt
5f7bd68149 i965: Add support for gl_FrontFacing to the new FS backend. 
Fixes:
glsl1-gl_FrontFacing var (1)
glsl1-gl_FrontFacing var (2)
 2010-09-28 10:10:44 -07:00
Eric Anholt
ef8e002c75 i965: Fix up part of my Sandybridge attributes support patch. 
I confused the array sizing for number of files for the number of regs
in a file.
 2010-09-28 10:10:42 -07:00
Eric Anholt
f1dba03056 i965: Fix all non-snb regression in the snb attribute interpolation commit. 
This apparently had never been tested elsewhere before being merged to
master.
 2010-09-28 10:10:42 -07:00
Eric Anholt
6bf12c8b73 i965: Add support for struct, array, and matrix uniforms to FS backend. 
Fixes 16 piglit cases.
 2010-09-28 09:33:31 -07:00
Eric Anholt
ba481f2046 i965: Add support for dereferencing structs to the new FS backend. 
Fixes: glsl1-struct(2)
 2010-09-28 09:33:31 -07:00
Eric Anholt
07fc8eed8f i965: Set the variable type when dereferencing an array. 
We don't set the type on the array virtual reg as a whole, so here's
the right place.

Fixes:
glsl1-GLSL 1.20 arrays
glsl1-temp array with constant indexing, fragment shader
glsl1-temp array with swizzled variable indexing
 2010-09-28 09:33:31 -07:00
Eric Anholt
719f84d9ab i965: Fix up the FS backend for the variable array indexing pass. 
We need to re-run channel expressions afterwards as it generates new
vector expressions, and we need to successfully support conditional
assignment (brw_CMP takes 2 operands, not 1).
 2010-09-28 09:33:30 -07:00
Eric Anholt
57edd7c5c1 i965: Fix valgrind complaint about base_ir for new FS debugging. 2010-09-28 09:33:30 -07:00
Eric Anholt
1723fdb3f0 i965: Apply the same set of lowering passes to new FS as to Mesa IR. 
While much of this we will want to support natively, this should make
the task of reaching the Mesa IR backend's quality easier.

Fixes:
glsl-fs-main-return.
 2010-09-28 09:33:30 -07:00
Eric Anholt
e10508812a i965: Actually track the "if" depth in loop in the new FS backend. 
Fixes:
glsl-fs-if-nested-loop.
 2010-09-28 09:33:30 -07:00
Eric Anholt
fceb78e3cc i965: Fix negation in the new FS backend. 
Fixes:
glsl1-Negation
glsl1-Negation2
 2010-09-28 09:33:30 -07:00
Jerome Glisse
7ee8fa0421 r600g: switch to new design 
New design seems to be on parity according to piglit,
make it default to get more exposure and see if there
is any show stopper in the coming days.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
 2010-09-28 11:37:30 -04:00
Jerome Glisse
b534eb16a2 r600g: fix remaining piglit issue in new design 
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
 2010-09-28 11:12:03 -04:00
Jerome Glisse
5a38cec7c8 r600g: use ptr for blit depth uncompress function 
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
 2010-09-28 09:51:08 -04:00
Christoph Bumiller
e0b93c5beb nv50: fix GP state bind and validate 2010-09-28 11:22:59 +02:00
Dave Airlie
175261a1f1 r600g: on evergreen the centroid isn't set in this register. 2010-09-28 19:02:46 +10:00
Zhenyu Wang
45b37c4b12 i965: fallback bitmap operation on sandybridge 
Need to bring back correct fb write with header to set pixel
write mask. Fallback for now.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
3074b61f64 i965: fix occlusion query on sandybridge 
Fix pipe control command for depth stall and PS_DEPTH_COUNT write.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
ec99833e92 i965: fix point sprite on sandybridge 
Need to set point sprite function in fixed SF state now on sandybridge.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
4b6b0bf24a i965: fix scissor state on sandybridge 
Fix incorrect scissor rect struct and missed scissor state pointer
setting for sandybridge.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
3f3059fcc0 i965: enable polygon offset on sandybridge 
Depth offset function is moved to SF stage on sandybridge.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
15a8e7ec90 i965: fix pixel w interpolation on sandybridge 2010-09-28 15:58:21 +08:00
Zhenyu Wang
85fa900b93 i965: don't do calculation for delta_xy on sandybridge 
Sandybridge doesn't have Xstart/Ystart in payload header.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
c58bf2cee5 i965: only allow SIMD8 kernel on sandybridge now 
Until we fixed SIMD16 kernel, force to SIMD8 on sandybridge now.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
18c3b754f9 i965: sandybridge pipe control workaround before write cache flush 
Must issue a pipe control with any non-zero post sync op before
write cache flush = 1 pipe control.
 2010-09-28 15:58:21 +08:00
Zhenyu Wang
c8033f1b1e i965: Add all device ids for sandybridge 2010-09-28 15:58:20 +08:00
Zhenyu Wang
81aae67e58 i965: fix const register count for sandybridge 
Sandybridge's PS constant buffer payload size is decided from
push const buffer command, incorrect size would cause wrong data
in payload for position and vertex attributes. This fixes coefficients
for tex2d/tex3d.
 2010-09-28 15:58:20 +08:00
Zhenyu Wang
956f866030 i965: Fix sampler on sandybridge 
Sandybridge has not much change on texture sampler with Ironlake.
 2010-09-28 15:58:20 +08:00
Zhenyu Wang
c5a3b25bb9 i965: fix jump count on sandybridge 
Jump count is for 64bit long each, so one instruction requires 2
like on Ironlake.
 2010-09-28 15:58:20 +08:00
Zhenyu Wang
9c39a9fcb2 i965: VS use SPF mode on sandybridge for now 
Until conditional instructions were fixed, use SPF mode instead for now.
 2010-09-28 15:58:20 +08:00