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Author SHA1 Message Date
Emma Anholt
99f31785a2 tu: Template tu6_emit_msaa() by CHIP. 
This gets us the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:56 +00:00
Emma Anholt
22a8475151 tu: Template update_vsc_pipe by CHIP. 
This lets us use non-deprecated reg packing, and fixes incorrect emitting
of 0D08 on 6xx that was introduced in 0cf27a7236 ("tu: Clear
`VSC_UNKNOWN_0D08` on A7XX")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:55 +00:00
Emma Anholt
17e47f4dff tu: Template fdm_apply_store_coords() by CHIP. 
Gets the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:55 +00:00
Emma Anholt
339c3c7970 tu: Use non-deprecated reg packing in tu6_setup_streamout()'s CRBs. 
This gets us the right registers on a8xx.  We can clean this up later with
the CRB builder.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:54 +00:00
Emma Anholt
7555600cc8 tu: Template tu_CmdBindIndexBuffer2KHR by CHIP. 
This gets us the right reg on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:54 +00:00
Emma Anholt
2f3ebc4f46 tu: Template tu_CmdBindTransformFeedbackBuffersEXT by CHIP. 
Gets the right regs for reg packing on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:54 +00:00
Emma Anholt
bfbc625f79 tu: Template tu_CmdBeginTransformFeedbackEXT() by CHIP. 
Gets the right regs for reg packing on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:53 +00:00
Emma Anholt
b69aa77456 tu: Template r2d_coords by CHIP. 
Gets us the right regs on 8xx

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:53 +00:00
Emma Anholt
b1a2757097 tu: Template tu7_emit_tile_render_begin_regs by CHIP. 
Gets us the right reg on 8xx

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:52 +00:00
Emma Anholt
e6a3699bf3 tu: Template tu6_build_depth_plane_z_mode by CHIP. 
Gets us the right reg on 8xx for GRAS_SU_DPETH_PLANE_CNTL.  I used a reg
pack function on the RB reg too, for consistency.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:52 +00:00
Emma Anholt
00bf0907e4 tu: Use tu_cs_emit_regs() for SU_POLY_OFFSET setup. 
This gets us the right regs on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:51 +00:00
Emma Anholt
35e5be2bed tu: Template tu6_emit_rt_workaround() by CHIP. 
This lets us set the right registers on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:51 +00:00
Emma Anholt
4439101dd3 tu: Template tu6_emit_window_scissor by CHIP. 
This lets us set the right registers on 8xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:50 +00:00
Emma Anholt
21e6c68bd1 tu: Use a register pack for VPC_PS_CNTL. 
Prep for dropping deprecated pack support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38796>
 2025-12-04 22:17:50 +00:00
Yiwei Zhang
b42d7c3809 ci: uprev virglrenderer 
This brings in latest virglrenderer that supports recently added venus
extensions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38800>
 2025-12-04 21:38:54 +00:00
Aitor Camacho
273f668520 wsi/metal: Fix blit_imate_to_image's pool selection for cmd buffer alloc
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Fixes: 39a7d65113 ("wsi/metal: Backend addition for drivers built on top of Metal")

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38785>
 2025-12-04 20:08:02 +00:00
Aitor Camacho
a547c6306a wsi/metal: Fix command buffer release at destroy 
Fixes: 39a7d65113 ("wsi/metal: Backend addition for drivers built on top of Metal")

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38785>
 2025-12-04 20:08:02 +00:00
José Roberto de Souza
49adffb0c0 iris: Rename iris_binding_table::sizes to iris_binding_table::surf_count 
This better reflect the usage of this array.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
José Roberto de Souza
e551c8d302 iris: Move code to emit push constants to its own function 
This allow us to reduce a bit the size of iris_upload_dirty_render_state().

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
José Roberto de Souza
3dda6b05e0 iris: Improve iris_emit_binding_tables() 
Moving all 3 for loops into a single one and populating binding tables before
emit it, the last part has no side effect but when reading the code it makes
more sense to populate binding table then emit it.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
José Roberto de Souza
d4658ddb73 iris: Move code to emit binding tables to its own function 
This allow us to reduce a bit the size of iris_upload_dirty_render_state() and
in next patches some improvements to this new function will be done.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38790>
 2025-12-04 19:43:21 +00:00
Aitor Camacho
5b039e0996 kk: Expose more features/extensions we already support
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Extensions:
- VK_KHR_load_store_op_none
- VK_KHR_map_memory2
- VK_EXT_load_store_op_none

Features:
- fullDrawIndexUint32
- inheritedQueries
- shaderStorageImageExtendedFormats

Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38783>
 2025-12-04 18:21:02 +00:00
Aitor Camacho
2e62777e0d kk: Apply robustness only when requested 
When lowering IO, we would always lower UBOs and SSBOs with robustness
enabled. This change only applies robustness if requested by the user.

Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38784>
 2025-12-04 18:04:56 +00:00
Aitor Camacho
48555926ac kk: Guard writes after fragment demote 
Required for M1 and M2 chips since they don't demote fragments.

Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38784>
 2025-12-04 18:04:56 +00:00
Emma Anholt
9e145f33cb ir3: Drop old comment about ldg vectorization limitation. 
We've looked at it again, and concluded that there's just no way that LDG
crossing a boundary could be OK in the components-are-read case but bad in
the components-are-not-read case, and this must have been papering over
something else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38704>
 2025-12-04 17:18:50 +00:00
Emma Anholt
24cd5088ca ir3: Perform vectorization on ldg/stg just like other memory access. 
shader-db effect comes from (perhaps older vkd3d?) DX12 fossils.  It sure
cleans up BDA CTS testcases, too.

Totals:
MaxWaves: 22151808 -> 22485222 (+1.51%); split: +1.51%, -0.06%
Instrs: 397754007 -> 396485642 (-0.32%); split: -0.41%, +0.10%
CodeSize: 990135656 -> 916286528 (-7.46%); split: -7.64%, +0.00%
STPs: 234296 -> 218861 (-6.59%); split: -6.62%, +0.03%
LDPs: 171664 -> 155386 (-9.48%); split: -9.53%, +0.04%

Totals from 130513 (8.36% of 1560788) affected shaders:
MaxWaves: 1376826 -> 1710240 (+24.22%); split: +24.30%, -0.90%
Instrs: 57789492 -> 56521127 (-2.19%); split: -2.84%, +0.66%
CodeSize: 256430400 -> 182581272 (-28.80%); split: -29.51%, +0.01%
NOPs: 7619148 -> 8015627 (+5.20%); split: -2.42%, +7.79%
MOVs: 4971200 -> 3968352 (-20.17%); split: -21.62%, +1.37%
COVs: 683166 -> 661427 (-3.18%); split: -3.24%, +0.04%
Full: 2422659 -> 1886993 (-22.11%); split: -22.98%, +0.03%
(ss): 1410724 -> 1479394 (+4.87%); split: -3.24%, +8.43%
(sy): 611391 -> 674588 (+10.34%); split: -1.14%, +11.66%
(ss)-stall: 4930898 -> 5265129 (+6.78%); split: -3.37%, +10.29%
(sy)-stall: 24138107 -> 29357000 (+21.62%); split: -1.82%, +23.71%
STPs: 112159 -> 96724 (-13.76%); split: -13.83%, +0.07%
LDPs: 113355 -> 97077 (-14.36%); split: -14.43%, +0.07%
Preamble Instrs: 83269073 -> 46493442 (-44.16%); split: -45.32%, +0.01%
Early Preamble: 79 -> 87 (+10.13%)
Cat0: 8516132 -> 8878083 (+4.25%); split: -2.28%, +6.68%
Cat1: 5994766 -> 4973985 (-17.03%); split: -19.02%, +1.94%
Cat2: 22297064 -> 22240177 (-0.26%); split: -0.30%, +0.05%
Cat3: 13748284 -> 13748279 (-0.00%)
Cat6: 1337948 -> 780266 (-41.68%); split: -42.19%, +0.27%
Cat7: 3247729 -> 3252768 (+0.16%); split: -1.48%, +1.71%
Subgroup size: 9280960 -> 9524224 (+2.62%); split: +2.63%, -0.01%

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38704>
 2025-12-04 17:18:49 +00:00
Yogesh Mohan Marimuthu
f27b2b8d77 winsys/amdgpu,ac: get eop and csa size,alignment from kernel query
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:21 +00:00
Yogesh Mohan Marimuthu
f322bc8631 ac: update amdgpu_drm.h for uq metadata query info 
struct drm_amdgpu_info_uq_fw_areas is renamed to drm_amdgpu_info_uq_metadata.
query infor structure for compute and sdma is added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:20 +00:00
Samuel Pitoiset
b13003133d radv: add radv_cmd_state::emitted_rt_pipeline 
To stop abusing emitted_compute_pipeline for RT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset
7d4c49a271 radv: decouple RT and compute dispatches paths 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:01 +00:00
Samuel Pitoiset
fa225de793 radv: constify radv_gfx12_emit_buffered_regs() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:00 +00:00
Samuel Pitoiset
e3aac0d11f radv: remove redundant buffered regs emission for dispatches on GFX12+ 
It's already called few lines above.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38782>
 2025-12-04 16:08:00 +00:00
Samuel Pitoiset
069f60a4e7 radv: enable conservativeRasterizationPostDepthCoverage on GFX10+ when possible
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This seems to work just fine, except on NAVI21, NAVI22 and VANGOGH. It
might be the same issue as has_vrs_ds_export_bug but it's not documented
anywhere. That being said, the CTS tests that fail don't even export
depth or stencil from fragment shaders.

Do not enable this feature on these GPUs to be conservative.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38767>
 2025-12-04 14:16:15 +00:00
Samuel Pitoiset
d1386e167e radv: add support for computeDerivativeGroupQuads on < GFX12 
This was also supported by PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38771>
 2025-12-04 13:56:47 +00:00
Christian Gmeiner
6a8460297a lavapipe: Advertise variableMultisampleRate
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Everything is in place to support this feature already.

Passes:
 dEQP-VK.pipeline.pipeline_library.multisample.variable_rate.*

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38693>
 2025-12-04 10:33:53 +00:00
Karol Herbst
a255e2ca56 nir: add ACCESS to shared_uniform_block_intel 
intel_nir_blockify_uniform_loads simply overwrites the intrinsic for
load_shared, which leads to messed up indicies, e.g:
  "base=0, access=volatile, align_mul=4, align_offset=0
became:
  "base=0, align_mul=4, align_offset=4"

Fixes: 0dd09a292b ("nir: add ACCESS_ATOMIC")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38801>
 2025-12-04 10:01:52 +00:00
Eric Engestrom
21d21ac824 docs: add sha sum for 25.2.8
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38806>
 2025-12-04 08:53:39 +01:00
Eric Engestrom
da01adfd11 docs: add release notes for 25.2.8 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38806>
 2025-12-04 08:53:39 +01:00
Eric Engestrom
ef057f7ca0 docs: update calendar for 25.2.8 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38806>
 2025-12-04 08:53:39 +01:00
Icenowy Zheng
46b97da60b pvr: fix PVR_DEBUG=info when running w/o KHR_display 
When running w/o KHR_display enabled, the display device node won't be
initlaized, and the information dump routine will terminate because of
this.

Fix this by not bailing out and not trying to print display device
compatible strings.

Fixes: 8825c91dcb ("pvr: Make display node optional")
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38787>
 2025-12-04 07:27:55 +00:00
Dylan Baker
a372d39609 docs: update calendar for 25.3.1
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38804>
 2025-12-04 06:33:28 +00:00
Dylan Baker
79b32de5bf docs: Add checksums for 25.3.1 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38804>
 2025-12-04 06:33:28 +00:00
Dylan Baker
a9dd1954fa docs: add release notes for 25.3.1 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38804>
 2025-12-04 06:33:28 +00:00
Pavel Ondračka
1642781673 r300/ci: update expectations 
Fallout from 60e115dedf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38797>
 2025-12-04 05:50:10 +00:00
Timothy Arceri
b75cd07265 util/driconf: add Cursemark workaround
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Fixes gpu hang on radeonsi and corrupt rendering on iris.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14392
Cc: mesa-stable

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38777>
 2025-12-03 23:58:15 +00:00
Connor Abbott
d5498240ac spirv: Remove view_index_is_input
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The last user was removed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38793>
 2025-12-03 22:52:29 +00:00
Connor Abbott
63a38b945d tu: Call nir_lower_sysvals_to_varyings once 
Remove the early call to nir_lower_sysvals_to_varyings. This guarantees
that we only call it after lower_system_values has replaced the
variables with intrinsics. It turns out that a sequence like this
doesn't work:

1. shader declares Layer builtin as a signed integer
2. nir_lower_sysvals_to_varyings turns it into a varying (but keeps the
  signed integer type)
3. nir_lower_input_attachments (or some other pass) creates a
  nir_load_layer_id intrinsic.
4. nir_lower_sysvals_to_varyings is called again, and when creating the
  varying variable it passes an unsigned type to
  nir_get_variable_with_location(), which asserts because there is
  already a signed integer variable.

By making lower_sysvals_to_varyings happen late for layer, we can avoid
this happening by lowering away the variable before (2).

Fixes: 5bbbf5cf9b ("tu: Set use_layer_id_sysval for nir_lower_input_attachments")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38793>
 2025-12-03 22:52:29 +00:00
Connor Abbott
4cfa188db6 tu: Stop setting view_index_is_input 
glslang apparently emits ViewID as a signed integer. If other passes
generate a sysval then lower_sysvals_to_varyings() tries to create an
variable with unsigned type and asserts when the preexisting varying's
type doesn't match the type it expects. Just make ViewID a sysval and
lower it in lower_sysvals_to_varyings() to avoid this and simplify the
SPIR-V parser.

Fixes: 5bbbf5cf9b ("tu: Set use_layer_id_sysval for nir_lower_input_attachments")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38793>
 2025-12-03 22:52:28 +00:00
Marek Olšák
e14f8ee0e4 nir/has_divergent_loop: require divergence metadata, check all function impls
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instead of forcing callers to call nir_divergence_analysis

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38597>
 2025-12-03 20:14:18 +00:00
Faith Ekstrand
d0b83dd7ce pan: Move pan_compile_shader to pan_compiler.c
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Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38788>
 2025-12-03 18:28:45 +00:00