Commit graph

15202 commits

Author SHA1 Message Date
Caio Oliveira
e6022281f2 intel/elk: Rename files to use elk prefix
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:31 +00:00
Caio Oliveira
b02712efc2 intel/elk: Remove DPAS lowering
This is meant for Gfx9+.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:31 +00:00
Caio Oliveira
b743ab7acc intel/elk: Remove stages not used in Gfx8-
OpenCL, Mesh and RayTracing stages are not supported, so removing them
and related code.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:31 +00:00
Caio Oliveira
8a57012ff4 intel/elk: Use common code in intel/compiler
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:30 +00:00
Caio Oliveira
dcf29202d4 intel/elk: Remove a bunch of files that don't apply for Gfx8-
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:30 +00:00
Caio Oliveira
06b553f02c intel/elk: Remove compiler specific devinfo hash
This more coarse-grained hash information for compiler (vs. full
devinfo), used only by Iris and Anv, and relevant for more recent
platforms.  Remove it from elk.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:30 +00:00
Caio Oliveira
0083585fc5 intel/elk: Compile ELK library, tests and tools
For now is not linked to any driver.  The tools were renamed to use elk
prefix to avoid conflicting with the brw ones.  The run-test.py script
was also updated due to that change.

Before the new compiler can be linked together with the old (going to be
done for Iris and other tools), the symbol conflicts need to be fixed
first.  This will happen in a later commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:30 +00:00
Caio Oliveira
d44462c08d intel/elk: Fork Gfx8- compiler by copying existing code
Based on code from commit c3ceec6cd8.

Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
2024-02-24 00:24:30 +00:00
Sagar Ghuge
c3244135fa anv: Set timestampValidBits to 64bits
On Xe2+, timestamp register can hold value upto 64-bit.

This change also fixes the timestamp related tests on Xe2 platform.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27713>
2024-02-22 17:58:38 +00:00
Lionel Landwerlin
fa34241932 intel/ci: bump anv/tgl fraction to 6
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27693>
2024-02-22 08:30:32 +00:00
Lionel Landwerlin
da5a6d185c ci/anv: add more testing for optimization paths
Anv implements optimization paths for large numbers of queries
clears/copies and indirect draws.

We would like to make sure those don't break.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27693>
2024-02-22 08:30:32 +00:00
Iván Briano
e3d4897dfe anv: flush query clears for all gens
Fixes: f733215c12 ("anv: enable query clear/copy using shaders on MTL/ARL")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27741>
2024-02-22 01:45:45 +00:00
Paulo Zanoni
2526308dcd anv/sparse: allow binding operations to match the resource size
The resource size doesn't need to match the binding granularity. For
example, if the user wants to create a 32kb buffer, Anv will require
its memory to have 64kb, but the buffer size will still be the
original 32kb. And the spec says:

  VUID-VkSparseMemoryBind-size-01100:
    "size must be less than or equal to the size of the resource minus
     resourceOffset"
  VUID-VkSparseMemoryBind-size-01102:
    "size must be less than or equal to the size of memory minus
     memoryOffset"

So when binding such buffer, size should actually be the lesser of the
two values: 32kb, and we have to accept that. Since our binding
granularity is 64kb, we're safe to simply extend the requested size to
match our binding granularity, since we already require the memory to
be appropriately sized.

None of this is exercised by dEQP. This was caught by
piglit/arb_sparse_buffer-basic using Zink.

Testcase: piglit/arb_sparse_buffer-basic
Issue: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10220
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26410>
2024-02-21 22:58:42 +00:00
Paulo Zanoni
a501a840a3 anv/sparse: add an extra step before anv_sparse_bind_resource_memory()
I need to add some sparse-related checks that require having the
anv_buffer and anv_image, and putting them directly inside
anv_queue_submit_sparse_bind_locked() doesn't feel like the right
thing to do. Here we change the interface so now we have
anv_sparse_bind_buffer() and anv_sparse_bind_image_opaque() as the
main interface into anv_sparse.c, so they both can call the lower
level anv_sparse_bind_resource_memory() function.

In the next patch we'll be adding changing the code of the functions
we just created, justifying their addition.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26410>
2024-02-21 22:58:42 +00:00
Karol Herbst
83895d4025 intel: Only build shaders with anv and iris
This allows crocus and hasvk to be built without needing any of the OpenCL
stuff.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10634
Fixes: b52e25d3a8 ("anv: rewrite internal shaders using OpenCL")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27663>
2024-02-21 20:53:36 +00:00
Karol Herbst
6474f8c2ce clc: include opencl-c.h for extensions needing it
This also allows tools build on clc to drop their workaround to include
it themselves. Rusticl might need it once it supports extensions which
need this file pulled in.

Later if the need to include it changes based on llvm version, we can
easily handle this in clc.

The main reason to include it only conditionally is the massively
reduction in compilation time. It also removes the mental burden from
users of clc to deal with any of this themselves.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10633
Fixes: 37a1346347 ("meson: remove opencl-external-clang-headers option and rely on shared-llvm")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27663>
2024-02-21 20:53:36 +00:00
José Roberto de Souza
341d0fcbf6 intel/tools/error_decode: Detect and split error dump file parsing by KMD
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27728>
2024-02-21 18:10:54 +00:00
José Roberto de Souza
1b07bb12d3 intel/tools/error_decode: Add support to search for Xe KMD error dumps
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27728>
2024-02-21 18:10:54 +00:00
José Roberto de Souza
77484ab6cf intel/tools/error_decode: Simply error message handling
In the code path without arguments it tries 3 different paths and error
messages are overwritten one by other, in this case any of those
error messages are irrelevant.

For the code path with arguments is similar, as it already have a
fprintf(stderr) in the caller of open_error_state_file().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27728>
2024-02-21 18:10:54 +00:00
José Roberto de Souza
70e2384f8f intel/tools/error_decode: Add function to try to open error dump file
Just to simply a bit open_error_state_file().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27728>
2024-02-21 18:10:54 +00:00
José Roberto de Souza
7cd677c491 intel/common: Remove more i915_drm.h includes from common code
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27728>
2024-02-21 18:10:54 +00:00
José Roberto de Souza
1b61786ac7 intel: Move intel_define.h to i915/intel_define.h
This file defines i915 context priorities, all users in Iris and ANV
have moved to i915 specific files, so the only remaining for this file
is move it to i915 folder so it do not gets included in common code
by mistake.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27728>
2024-02-21 18:10:54 +00:00
Matt Turner
9f32e1a489 anv/drirc: Add option to control implicit sync on external BOs
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10546
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27704>
2024-02-21 17:19:26 +00:00
Caio Oliveira
cfc8cf198c intel/meson: Fix warning about broken str.format
Meson complains:

../src/intel/decoder/meson.build:67: DEPRECATION: Project uses feature that was always broken, and is now deprecated since '1.3.0': str.format: Value other than strings, integers, bools, options, dictionaries and lists thereof..

So instead of trying to format a file, change gentest_xml to store just
the string.  Need to adapt genxml_path to consider the current source
dir, but everything else works like before.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27706>
2024-02-21 17:02:04 +00:00
Caio Oliveira
8f38757067 intel/meson: Remove usage of meson.source_root and meson.build_root
Both are deprecated and the alternatives are already being used in
the project, so start using those here too:

```
../src/intel/shaders/meson.build:64: WARNING: Project targets '>= 1.1.0' but uses feature deprecated since '0.56.0': meson.source_root. use meson.project_source_root() or meson.global_source_root() instead.
../src/intel/shaders/meson.build:65: WARNING: Project targets '>= 1.1.0' but uses feature deprecated since '0.56.0': meson.build_root. use meson.project_build_root() or meson.global_build_root() instead.
```

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27706>
2024-02-21 17:02:04 +00:00
Lionel Landwerlin
137b7e874f anv: disable Wa_16013994831
We've implemented another workaround completely disabling high
priority preemption.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e6e320fc79 ("anv: make Wa_16013994831 to use intel_needs_workaround")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27716>
2024-02-21 11:39:50 +00:00
Kenneth Graunke
c12300844d intel/fs: Don't rely on CSE for VARYING_PULL_CONSTANT_LOAD
In the past, we didn't have a good solution for combining scalar loads
with a variable index plus a constant offset.  To handle that, we took
our load offset and rounded it down to the nearest vec4, loaded an
entire vec4, and trusted in the backend CSE pass to detect loads from
the same address and remove redundant ones.

These days, nir_opt_load_store_vectorize() does a good job of taking
those scalar loads and combining them into vector loads for us, so we
no longer need to do this trick.  In fact, it can be better not to:
our offset need only be 4 byte (scalar) aligned, but we were making it
16 byte (vec4) aligned.  So if you wanted to load an unaligned vec2,
we might actually load two vec4's (___X | Y___) instead of doing a
single load at the starting offset.

This should also reduce the work the backend CSE pass has to do,
since we just emit a single VARYING_PULL_CONSTANT_LOAD instead of 4.

shader-db results on Alchemist:
- No changes in SEND count or spills/fills
- Instructions: helped 95, hurt 100, +/- 1-3 instructions
- Cycles: helped 3411 hurt 1868, -0.01% (-0.28% in affected)
- SIMD32: gained 5, lost 3

fossil-db results on Alchemist:
- Instrs: 161381427 -> 161384130 (+0.00%); split: -0.00%, +0.00%
- Cycles: 14258305873 -> 14145884365 (-0.79%); split: -0.95%, +0.16%
- SIMD32: Gained 42, lost 26

- Totals from 56285 (8.63% of 652236) affected shaders:
- Instrs: 13318308 -> 13321011 (+0.02%); split: -0.01%, +0.03%
- Cycles: 7464985282 -> 7352563774 (-1.51%); split: -1.82%, +0.31%

From this we can see that we aren't doing more loads than before
and the change is pretty inconsequential, but it requires less
optimizing to produce similar results.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27568>
2024-02-20 23:16:27 -08:00
Caio Oliveira
8ae528331c intel/compiler: Use "intel" prefix for walk_order enum
Will be used later in non-brw specific code in Iris.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27646>
2024-02-21 00:38:35 +00:00
Kenneth Graunke
1497f4e0c2 intel/fs: Don't include sync.nop in instruction count statistics
With the advent of software scoreboarding, we emit sync instructions
in various places to synchronize the execution pipelines.  This results
in assembly being littered with a bunch of sync.nop instructions.  That
means that when you reorder anything in the program, the scoreboarding
changes, and the number of sync.nops can vary wildly - even if the code
isn't really materially better or worse.  This makes it hard to use
tools like shader-db or fossil-db on post-Icelake platforms.

For now, exclude sync.nops from the instruction count statistic.  One
day we may want to consider improving the software scoreboarding pass
to emit fewer redundant sync.nop instructions, at which point tracking
this as a separate stat might be useful.  For now though, it's simply
cluttering and confusing our results.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27701>
2024-02-20 22:26:09 +00:00
Caio Oliveira
078dbc4d33 anv: Remove lower_atomics from storage image lowering opts
The code only applies to Gfx <= 7.5, so it is a no-op.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27638>
2024-02-20 19:47:07 +00:00
Lionel Landwerlin
0eb3c850c6 intel/clc: workaround LLVM17 opaque pointers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: b52e25d3a8 ("anv: rewrite internal shaders using OpenCL")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27637>
2024-02-20 14:41:43 +00:00
Lionel Landwerlin
62baa4df5f intel/clc: lower temp function/shader variables together
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 4fd7495c69 ("intel/clc: add ability to output NIR")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27637>
2024-02-20 14:41:43 +00:00
Lionel Landwerlin
19aeb274e6 genxml: generate opencl temporary variables with private qualifier
To avoid generic pointers, makes the NIR prints a bit more readable.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 41b2ed65 ("genxml: generate opencl packing headers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27637>
2024-02-20 14:41:43 +00:00
Lionel Landwerlin
96ab1d65cc anv: fix emission of Wa_14015055625
When moving the static part, I missed that the
pipeline->primitive_id_override field isn't set yet when we check it
to emit 3DSTATE_TE.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1e081bd680 ("anv: split 3DSTATE_TE packing between static & dynamic parts")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27692>
2024-02-20 09:49:00 +00:00
Lionel Landwerlin
63676ed502 anv: fix Wa_16013994831 macros
The commit that switched to the WA framework forgot to update one of
the ifdef section.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e6e320fc79 ("anv: make Wa_16013994831 to use intel_needs_workaround")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27676>
2024-02-19 12:48:33 +00:00
Lionel Landwerlin
682c23aa06 anv: remove unused definition
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Lionel Landwerlin
27a7c5447d anv: reenable ANV_ALWAYS_BINDLESS
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Lionel Landwerlin
dbee85713f anv: factor out descriptor buffer flushing
Take the opportunity to fix the flush of the descriptor buffer surface
when needed. Previously we would only flush it if the shader used one
of the push descriptor.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Lionel Landwerlin
cf193af762 anv: fixup push descriptor shader analysis
There are a couple mistakes here :

   - using a bitfield as an index to generate a bitfield...

   - in anv_nir_push_desc_ubo_fully_promoted(), confusing binding
     table access of the descriptor buffer with actual descriptors

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Caio Oliveira
5feb326d80 intel/isl: Include compiler generic header
Instead of including a brw-specific one.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
ae50ac46d1 intel: Remove brw_ prefix from process debug function
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
c773898f39 intel/compiler: Rename brw_gfx_ver_enum.h to intel_gfx_ver_enum.h
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
d8f9a05f32 intel/compiler: Rename the passes and files related to intel_nir.h
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
dc76cfc781 intel/compiler: Collect NIR-only passes in intel_nir.h
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Sagar Ghuge
24db040a49 anv: Drop warnings for engine initialization failure
We don't have to spit out warnings for the end users. For compute if we
fail to initialize, we are falling back to render for compute operation,

Anyway end-user applications can query what the engines/queues are
supported based on that they can choose to use a specific queue.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27660>
2024-02-16 20:48:17 +00:00
Caio Oliveira
805d45e916 intel/decoder: Move decoder to a separate module
Depends on both intel/common and intel/compiler.  Breaks circular
dependency between these two modules.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27647>
2024-02-16 16:37:31 +00:00
José Roberto de Souza
19439624d9 anv: Use DRM_XE_VM_BIND_OP_UNMAP_ALL to unbind whole bos
For non-sparse usage there is no difference between
DRM_XE_VM_BIND_OP_UNMAP_ALL and DRM_XE_VM_BIND_OP_UNMAP but for sparse
the same bo can be bound to more than one virtual address.

Then in a case like:
img = vkCreateImage()
mem = vkAllocateMemory()
vkQueueBindSparse(img, mem)
vkFreeMemory(mem)

Note that the sparse VMA bind still points to the closed bo(done in
vkFreeMemory()), but with DRM_XE_VM_BIND_OP_UNMAP_ALL all VMAs
over the bos are removed.

Access to a unbound VMA has a defined behavior(page fault) while
access to a bound VMA without backing gem/bo don't have defined
behavior.

Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27601>
2024-02-16 13:43:45 +00:00
Mark Janes
08176d9d16 intel/tools: add shader compiler hash key to json devinfo format
Offline shader compilation will use json as the source configuration
to accurately instantiate mesa for target hardware.  Similar platforms
generate identical shader binaries even though intel_device_info
differs inconsequenially.

Include the shader compilation hash key to device info json files, so
these platforms can be deduplicated.

Closes: #6746

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
2024-02-15 16:59:25 -08:00
Mark Janes
aa649dfa5f intel/tools: move intel_dev_info to intel/tools
This is a more sensible home for intel_dev_info.

Offline shader compilation will take intel_dev_info json files as
input.  For that use case, the shader compiler hash value is needed in
the json file.

intel_dev_info will depend on intel/compiler, and must be located in
intel/tools to break a circular meson dependency.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
2024-02-15 16:59:15 -08:00
Mark Janes
9b1ae760a8 anv: use intel_device_info to set device UUID
For anv, use the intel device info hash function instead of
device PCI ID when generating a UUID for the pipeline cache.

PCI ID can vary between on devices which are comparable from the
perspective of the shader compiler.  A more precise key eliminates
redundant entries in a multiplatform shader cache.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
2024-02-15 16:58:20 -08:00