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intel/elk: Remove DPAS lowering
This is meant for Gfx9+. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
b743ab7acc
commit
b02712efc2
3 changed files with 0 additions and 310 deletions
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@ -5990,9 +5990,6 @@ fs_visitor::optimize()
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validate();
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if (compiler->lower_dpas)
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OPT(brw_lower_dpas, *this);
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OPT(split_virtual_grfs);
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/* Before anything else, eliminate dead code. The results of some NIR
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@ -1,306 +0,0 @@
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/*
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* Copyright 2023 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include "brw_fs.h"
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#include "brw_fs_builder.h"
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using namespace brw;
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static void
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f16_using_mac(const fs_builder &bld, fs_inst *inst)
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{
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/* We only intend to support configurations where the destination and
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* accumulator have the same type.
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*/
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if (!inst->src[0].is_null())
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assert(inst->dst.type == inst->src[0].type);
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assert(inst->src[1].type == BRW_REGISTER_TYPE_HF);
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assert(inst->src[2].type == BRW_REGISTER_TYPE_HF);
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const brw_reg_type src0_type = inst->dst.type;
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const brw_reg_type src1_type = BRW_REGISTER_TYPE_HF;
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const brw_reg_type src2_type = BRW_REGISTER_TYPE_HF;
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const fs_reg dest = inst->dst;
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fs_reg src0 = inst->src[0];
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const fs_reg src1 = retype(inst->src[1], src1_type);
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const fs_reg src2 = retype(inst->src[2], src2_type);
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const unsigned dest_stride =
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dest.type == BRW_REGISTER_TYPE_HF ? REG_SIZE / 2 : REG_SIZE;
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for (unsigned r = 0; r < inst->rcount; r++) {
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fs_reg temp = bld.vgrf(BRW_REGISTER_TYPE_HF, 1);
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for (unsigned subword = 0; subword < 2; subword++) {
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for (unsigned s = 0; s < inst->sdepth; s++) {
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/* The first multiply of the dot-product operation has to
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* explicitly write the accumulator register. The successive MAC
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* instructions will implicitly read *and* write the
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* accumulator. Those MAC instructions can also optionally
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* explicitly write some other register.
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*
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* FINISHME: The accumulator can actually hold 16 HF values. On
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* Gfx12 there are two accumulators. It should be possible to do
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* this in SIMD16 or even SIMD32. I was unable to get this to work
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* properly.
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*/
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if (s == 0 && subword == 0) {
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const unsigned acc_width = 8;
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fs_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_REGISTER_TYPE_UD),
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inst->group % acc_width);
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if (bld.shader->devinfo->verx10 >= 125) {
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acc = subscript(acc, BRW_REGISTER_TYPE_HF, subword);
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} else {
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acc = retype(acc, BRW_REGISTER_TYPE_HF);
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}
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bld.MUL(acc,
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subscript(retype(byte_offset(src1, s * REG_SIZE),
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BRW_REGISTER_TYPE_UD),
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BRW_REGISTER_TYPE_HF, subword),
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component(retype(byte_offset(src2, r * REG_SIZE),
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BRW_REGISTER_TYPE_HF),
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s * 2 + subword))
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->writes_accumulator = true;
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} else {
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fs_reg result;
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/* As mentioned above, the MAC had an optional, explicit
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* destination register. Various optimization passes are not
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* clever enough to understand the intricacies of this
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* instruction, so only write the result register on the final
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* MAC in the sequence.
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*/
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if ((s + 1) == inst->sdepth && subword == 1)
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result = temp;
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else
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result = retype(bld.null_reg_ud(), BRW_REGISTER_TYPE_HF);
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bld.MAC(result,
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subscript(retype(byte_offset(src1, s * REG_SIZE),
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BRW_REGISTER_TYPE_UD),
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BRW_REGISTER_TYPE_HF, subword),
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component(retype(byte_offset(src2, r * REG_SIZE),
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BRW_REGISTER_TYPE_HF),
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s * 2 + subword))
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->writes_accumulator = true;
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}
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}
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}
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if (!src0.is_null()) {
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if (src0_type != BRW_REGISTER_TYPE_HF) {
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fs_reg temp2 = bld.vgrf(src0_type, 1);
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bld.MOV(temp2, temp);
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bld.ADD(byte_offset(dest, r * dest_stride),
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temp2,
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byte_offset(src0, r * dest_stride));
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} else {
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bld.ADD(byte_offset(dest, r * dest_stride),
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temp,
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byte_offset(src0, r * dest_stride));
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}
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} else {
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bld.MOV(byte_offset(dest, r * dest_stride), temp);
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}
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}
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}
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static void
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int8_using_dp4a(const fs_builder &bld, fs_inst *inst)
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{
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/* We only intend to support configurations where the destination and
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* accumulator have the same type.
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*/
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if (!inst->src[0].is_null())
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assert(inst->dst.type == inst->src[0].type);
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assert(inst->src[1].type == BRW_REGISTER_TYPE_B ||
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inst->src[1].type == BRW_REGISTER_TYPE_UB);
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assert(inst->src[2].type == BRW_REGISTER_TYPE_B ||
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inst->src[2].type == BRW_REGISTER_TYPE_UB);
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const brw_reg_type src1_type = inst->src[1].type == BRW_REGISTER_TYPE_UB
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? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
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const brw_reg_type src2_type = inst->src[2].type == BRW_REGISTER_TYPE_UB
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? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
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fs_reg dest = inst->dst;
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fs_reg src0 = inst->src[0];
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const fs_reg src1 = retype(inst->src[1], src1_type);
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const fs_reg src2 = retype(inst->src[2], src2_type);
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const unsigned dest_stride = REG_SIZE;
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for (unsigned r = 0; r < inst->rcount; r++) {
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if (!src0.is_null()) {
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bld.MOV(dest, src0);
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src0 = byte_offset(src0, dest_stride);
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} else {
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bld.MOV(dest, retype(brw_imm_d(0), dest.type));
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}
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for (unsigned s = 0; s < inst->sdepth; s++) {
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bld.DP4A(dest,
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dest,
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byte_offset(src1, s * REG_SIZE),
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component(byte_offset(src2, r * REG_SIZE), s))
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->saturate = inst->saturate;
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}
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dest = byte_offset(dest, dest_stride);
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}
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}
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static void
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int8_using_mul_add(const fs_builder &bld, fs_inst *inst)
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{
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/* We only intend to support configurations where the destination and
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* accumulator have the same type.
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*/
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if (!inst->src[0].is_null())
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assert(inst->dst.type == inst->src[0].type);
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assert(inst->src[1].type == BRW_REGISTER_TYPE_B ||
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inst->src[1].type == BRW_REGISTER_TYPE_UB);
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assert(inst->src[2].type == BRW_REGISTER_TYPE_B ||
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inst->src[2].type == BRW_REGISTER_TYPE_UB);
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const brw_reg_type src0_type = inst->dst.type;
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const brw_reg_type src1_type = inst->src[1].type == BRW_REGISTER_TYPE_UB
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? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
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const brw_reg_type src2_type = inst->src[2].type == BRW_REGISTER_TYPE_UB
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? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
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fs_reg dest = inst->dst;
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fs_reg src0 = inst->src[0];
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const fs_reg src1 = retype(inst->src[1], src1_type);
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const fs_reg src2 = retype(inst->src[2], src2_type);
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const unsigned dest_stride = REG_SIZE;
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for (unsigned r = 0; r < inst->rcount; r++) {
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if (!src0.is_null()) {
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bld.MOV(dest, src0);
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src0 = byte_offset(src0, dest_stride);
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} else {
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bld.MOV(dest, retype(brw_imm_d(0), dest.type));
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}
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for (unsigned s = 0; s < inst->sdepth; s++) {
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fs_reg temp1 = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
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fs_reg temp2 = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
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fs_reg temp3 = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
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const brw_reg_type temp_type =
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(inst->src[1].type == BRW_REGISTER_TYPE_B ||
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inst->src[2].type == BRW_REGISTER_TYPE_B)
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? BRW_REGISTER_TYPE_W : BRW_REGISTER_TYPE_UW;
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/* Expand 8 dwords of packed bytes into 16 dwords of packed
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* words.
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*
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* FINISHME: Gfx9 should not need this work around. Gfx11
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* may be able to use integer MAD. Both platforms may be
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* able to use MAC.
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*/
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bld.group(32, 0).MOV(retype(temp3, temp_type),
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retype(byte_offset(src2, r * REG_SIZE),
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inst->src[2].type));
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bld.MUL(subscript(temp1, temp_type, 0),
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subscript(retype(byte_offset(src1, s * REG_SIZE),
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BRW_REGISTER_TYPE_UD),
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inst->src[1].type, 0),
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subscript(component(retype(temp3,
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BRW_REGISTER_TYPE_UD),
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s * 2),
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temp_type, 0));
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bld.MUL(subscript(temp1, temp_type, 1),
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subscript(retype(byte_offset(src1, s * REG_SIZE),
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BRW_REGISTER_TYPE_UD),
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inst->src[1].type, 1),
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subscript(component(retype(temp3,
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BRW_REGISTER_TYPE_UD),
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s * 2),
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temp_type, 1));
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bld.MUL(subscript(temp2, temp_type, 0),
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subscript(retype(byte_offset(src1, s * REG_SIZE),
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BRW_REGISTER_TYPE_UD),
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inst->src[1].type, 2),
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subscript(component(retype(temp3,
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BRW_REGISTER_TYPE_UD),
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s * 2 + 1),
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temp_type, 0));
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bld.MUL(subscript(temp2, temp_type, 1),
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subscript(retype(byte_offset(src1, s * REG_SIZE),
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BRW_REGISTER_TYPE_UD),
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inst->src[1].type, 3),
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subscript(component(retype(temp3,
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BRW_REGISTER_TYPE_UD),
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s * 2 + 1),
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temp_type, 1));
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bld.ADD(subscript(temp1, src0_type, 0),
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subscript(temp1, temp_type, 0),
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subscript(temp1, temp_type, 1));
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bld.ADD(subscript(temp2, src0_type, 0),
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subscript(temp2, temp_type, 0),
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subscript(temp2, temp_type, 1));
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bld.ADD(retype(temp1, src0_type),
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retype(temp1, src0_type),
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retype(temp2, src0_type));
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bld.ADD(dest, dest, retype(temp1, src0_type))
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->saturate = inst->saturate;
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}
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dest = byte_offset(dest, dest_stride);
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}
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}
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bool
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brw_lower_dpas(fs_visitor &v)
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{
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bool progress = false;
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foreach_block_and_inst_safe(block, fs_inst, inst, v.cfg) {
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if (inst->opcode != BRW_OPCODE_DPAS)
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continue;
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const fs_builder bld = fs_builder(&v, block, inst).group(8, 0).exec_all();
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if (brw_reg_type_is_floating_point(inst->dst.type)) {
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f16_using_mac(bld, inst);
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} else {
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if (v.devinfo->ver >= 12) {
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int8_using_dp4a(bld, inst);
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} else {
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int8_using_mul_add(bld, inst);
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}
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}
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inst->remove(block);
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progress = true;
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}
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if (progress)
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v.invalidate_analysis(DEPENDENCY_INSTRUCTIONS);
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return progress;
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}
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@ -58,7 +58,6 @@ libintel_compiler_elk_files = files(
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'brw_fs.h',
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'brw_fs_live_variables.cpp',
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'brw_fs_live_variables.h',
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'brw_fs_lower_dpas.cpp',
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'brw_fs_lower_pack.cpp',
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'brw_fs_lower_regioning.cpp',
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'brw_fs_nir.cpp',
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