Commit graph

517 commits

Author SHA1 Message Date
José Roberto de Souza
f91de58818 anv: Add support to DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION
When this flag is set, it gives a hint to KMD to skip some operations around
compressed buffers, like copying the auxiliary buffer to smem during eviction.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38425>
2026-01-06 06:39:32 -08:00
Sushma Venkatesh Reddy
d1d4e3d530 brw: Add EU assembler support for float8
Decode logic in Gfx12+ has become complex with the new types, so Caio
suggested that we move to the table like other gens.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39007>
2025-12-19 00:09:53 +00:00
Lionel Landwerlin
e241e30986 anv: add a no-resource-barrier debug flag
Some checks are pending
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
2025-12-15 08:25:42 +00:00
Lionel Landwerlin
efe60d2940 intel: remove unused show_shader_stage debug option
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Michael Cheng <michael.cheng@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38869>
2025-12-10 20:32:09 +00:00
Calder Young
c0d809820f intel: Fix calculation of max_scratch_ids on fused devices
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The subslice IDs provided by the SR0.0 EU register are not adjusted to account
for fusing, so the upper bound max_scratch_ids can vary from device to device
depending on what specific slices were fused during manufacturing.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38689>
2025-11-29 15:10:29 +00:00
Yonggang Luo
0a32d5e6fd treewide: Use regexp to replace usage of setenv with os_set_option.
setenv\((.*), 1\);
=>
os_set_option($1, true);

setenv\((.*), 0\);
=>
os_set_option($1, false);

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38640>
2025-11-27 18:22:34 +00:00
Ian Romanick
d2e3707ecc brw: Eliminate redundant fills and spills
When the register allocator decides to spill a value, all writes to that
value are spilled and all reads are filled. In regions where there is
not high register pressure, a spill of a value may be followed by a fill
of that same file while the spilled register is still live. This
optimization pass finds these cases, and it converts the fill to a move
from the still-live register.

The restriction that the spill and the fill must have matching NoMask
really hampers this optimization. With the restriction removed, the pass
was more than 2x helpful.

v2: Require force_writemask_all to be the same for the spill and the fill.

v3: Use FIXED_GRF for register overlap tests. Since this is after
register allocation, the VGRF values will not tell the whole truth.

v4: Use brw_transform_inst. Suggested by Caio. The allows two of the
loops to be merged. Add brw_scratch_inst::offset instead of storing it
as a source. Suggested by Lionel.

v5: Add no-fill-opt debug option to disable optimizations. Suggested by
Lionel.

v6: Move a calculation outside a loop. Suggested by Lionel.

v7: Check that spill ranges overlap instead of just checking initial
offset. Zero shaders in fossil-db were affected, but some CTS with
spill_fs were fixed (e.g.,
dEQP-VK.subgroups.arithmetic.compute.subgroupmin_uint64_t_requiredsubgroupsize).
Suggested by Lionel.

v8: Add DEBUG_NO_FILL_OPT to debug_bits in
brw_get_compiler_config_value(). Noticed by Lionel.

shader-db:

Lunar Lake
total instructions in shared programs: 17249907 -> 17249903 (<.01%)
instructions in affected programs: 10684 -> 10680 (-0.04%)
helped: 2 / HURT: 0

total cycles in shared programs: 893092630 -> 893092398 (<.01%)
cycles in affected programs: 237320 -> 237088 (-0.10%)
helped: 2 / HURT: 0

total fills in shared programs: 1903 -> 1901 (-0.11%)
fills in affected programs: 110 -> 108 (-1.82%)
helped: 2 / HURT: 0

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
total instructions in shared programs: 19968898 -> 19968778 (<.01%)
instructions in affected programs: 33020 -> 32900 (-0.36%)
helped: 10 / HURT: 0

total cycles in shared programs: 885157211 -> 884925015 (-0.03%)
cycles in affected programs: 39944544 -> 39712348 (-0.58%)
helped: 8 / HURT: 2

total fills in shared programs: 4454 -> 4394 (-1.35%)
fills in affected programs: 2678 -> 2618 (-2.24%)
helped: 10 / HURT: 0

fossil-db:

Lunar Lake
Totals:
Instrs: 930445228 -> 929949528 (-0.05%)
Cycle count: 105195579417 -> 105126671329 (-0.07%); split: -0.07%, +0.00%
Spill count: 3495279 -> 3494400 (-0.03%)
Fill count: 6767063 -> 6520785 (-3.64%)

Totals from 43844 (2.17% of 2018922) affected shaders:
Instrs: 212614840 -> 212119140 (-0.23%)
Cycle count: 19151130510 -> 19082222422 (-0.36%); split: -0.39%, +0.03%
Spill count: 2831100 -> 2830221 (-0.03%)
Fill count: 6128316 -> 5882038 (-4.02%)

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 1001375893 -> 1001113407 (-0.03%)
Cycle count: 92746180943 -> 92679877883 (-0.07%); split: -0.08%, +0.01%
Spill count: 3729157 -> 3728585 (-0.02%)
Fill count: 6697296 -> 6566874 (-1.95%)

Totals from 35062 (1.53% of 2284674) affected shaders:
Instrs: 179819265 -> 179556779 (-0.15%)
Cycle count: 18111194752 -> 18044891692 (-0.37%); split: -0.41%, +0.04%
Spill count: 2453752 -> 2453180 (-0.02%)
Fill count: 5279259 -> 5148837 (-2.47%)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37827>
2025-11-26 17:20:13 +00:00
Lionel Landwerlin
ef5a0def76 intel/isl: add INTEL_DEBUG=noccs-modifier to disable CCS modifiers
Some checks are pending
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To help figure out whether a CCS related corruption is tied to
modifier setup or internal driver state tracking.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38382>
2025-11-13 09:52:27 +00:00
Tapani Pälli
9a71dcde1b intel/dev: update mesa_defs.json from internal database
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37975>
2025-11-04 05:17:30 +00:00
Jordan Justen
84a67b5ab4 intel/dev: Add NVL-S/U PCI IDs (with FORCE_PROBE required)
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Ref: bspec 74201
Ref: c002b1764e
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38020>
2025-10-23 21:47:29 +00:00
Jordan Justen
ac1a7e19e8 intel/dev: Add NVL-S/U device info
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38020>
2025-10-23 21:47:29 +00:00
Jordan Justen
84bba237ca intel/dev: Add INTEL_PLATFORM_NVL_U platform enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38020>
2025-10-23 21:47:28 +00:00
Sushma Venkatesh Reddy
44c1dcd0ed intel/dev: Add geometry, color and depth pipes count
Geometry, Color and Depth pipelines count are needed for collecting some
metrics from perfetto.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37072>
2025-10-23 16:59:09 +00:00
José Roberto de Souza
ad86a666ae anv: Add support for low latency hint on Xe KMD
This hint tells KMD and firmware to turn into low latency but high
power usage mode.
i915 already had it now it was implemented in Xe KMD.

Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33214>
2025-10-16 20:23:21 +00:00
José Roberto de Souza
0ba6a0a23b intel/dev: Add supports_low_latency_hint to intel_device_info
Lets query if this feature is supported only once, also in the next
patches support for this feature will be added to Xe KMD.

Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33214>
2025-10-16 20:23:21 +00:00
Nanley Chery
b709d7dd39 intel: Delete the has_illegal_ccs_values bool
This was only used in one location.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36383>
2025-10-06 13:50:39 +00:00
Tim Van Patten
f90e0f0797 intel: Convert getenv() to os_get_option()
Some checks are pending
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os_get_option() is a wrapper for getenv() that checks properties in
Android. It should be a no-op for other OS but will allow full use of
env vars in Android.

The environment variable names are automatically renamed by
os_get_option() and the order of precedence thus becomes:

1. getenv (non-Android)
2. debug.mesa.* (Android)
3. vendor.mesa.* (Android)
4. mesa.* (Android, as a fallback for older versions)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37587>
2025-09-25 17:01:18 -06:00
Caio Oliveira
f82d85a685 brw: Use debug archive file with INTEL_DEBUG=mda
Instead of dumping multiple files with the optimizer passes, write a single
archive file with all the contents.  The actual file is created
by the drivers, so later commits will actually enable the feature in
anv and iris.

This removes the use of INTEL_DEBUG=optimizer (and the corresponding
enum value) in brw.  That environment variable is still used by ELK --
which currently doesn't support mda.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29146>
2025-09-24 23:08:45 -07:00
Tapani Pälli
c65f5cd36d intel/dev: provide a helper to detect bmg g31 device
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966>
2025-08-26 19:35:33 +00:00
Qiang Yu
196569b1a4 all: rename gl_shader_stage to mesa_shader_stage
It's not only for GL, change to a generic name.

Use command:
  find . -type f -not -path '*/.git/*' -exec sed -i 's/\bgl_shader_stage\b/mesa_shader_stage/g' {} +

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
2025-08-06 10:28:40 +08:00
Antonio Ospite
ddf2aa3a4d build: avoid redefining unreachable() which is standard in C23
In the C23 standard unreachable() is now a predefined function-like
macro in <stddef.h>

See https://android.googlesource.com/platform/bionic/+/HEAD/docs/c23.md#is-now-a-predefined-function_like-macro-in

And this causes build errors when building for C23:

-----------------------------------------------------------------------
In file included from ../src/util/log.h:30,
                 from ../src/util/log.c:30:
../src/util/macros.h:123:9: warning: "unreachable" redefined
  123 | #define unreachable(str)    \
      |         ^~~~~~~~~~~
In file included from ../src/util/macros.h:31:
/usr/lib/gcc/x86_64-linux-gnu/14/include/stddef.h:456:9: note: this is the location of the previous definition
  456 | #define unreachable() (__builtin_unreachable ())
      |         ^~~~~~~~~~~
-----------------------------------------------------------------------

So don't redefine it with the same name, but use the name UNREACHABLE()
to also signify it's a macro.

Using a different name also makes sense because the behavior of the
macro was extending the one of __builtin_unreachable() anyway, and it
also had a different signature, accepting one argument, compared to the
standard unreachable() with no arguments.

This change improves the chances of building mesa with the C23 standard,
which for instance is the default in recent AOSP versions.

All the instances of the macro, including the definition, were updated
with the following command line:

  git grep -l '[^_]unreachable(' -- "src/**" | sort | uniq | \
  while read file; \
  do \
    sed -e 's/\([^_]\)unreachable(/\1UNREACHABLE(/g' -i "$file"; \
  done && \
  sed -e 's/#undef unreachable/#undef UNREACHABLE/g' -i src/intel/isl/isl_aux_info.c

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36437>
2025-07-31 17:49:42 +00:00
Jordan Justen
bca1acbb42 intel/dev: Add WCL PCI IDs
Tested with:

commit 3a252ff9d8b6dc22b20463bfcb31a4e8992b0e8f
Merge: 9800bf6fae3b 11895f375939
Author: Simona Vetter <simona.vetter@ffwll.ch>
Date:   Fri Jul 11 11:25:34 2025 +0200

Note that the kernel treats WCL similar to PTL, so 94de1dfd4729
("drm/xe/ptl: Drop force_probe requirement") also removed the
force_probe for WCL.

Backport-to: 25.1
Ref: 3c0f211bc8fc ("drm/xe: Add Wildcat Lake device IDs to PTL list")
Ref: 94de1dfd4729 ("drm/xe/ptl: Drop force_probe requirement")
Ref: drm/drm-next 3a252ff9d8b6dc22b20463bfcb31a4e8992b0e8f
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36148>
2025-07-21 21:22:05 +00:00
Jordan Justen
8b771e8937 intel/dev: Add WCL device info
Backport-to: 25.1
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36148>
2025-07-21 21:22:05 +00:00
Jordan Justen
ffabca9101 intel/dev/mesa_defs.json: Add WCL WA entries
Backport-to: 25.1
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36148>
2025-07-21 21:22:05 +00:00
Jordan Justen
23bc204faa intel/dev: Add WCL platform enum
Backport-to: 25.1
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36148>
2025-07-21 21:22:05 +00:00
Caio Oliveira
887642b0f2 intel: Add INTEL_DEBUG=no-vrt
Some checks are pending
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Add support for disabling the VRT (Variable Register Thread) feature.
The strategy here is to force the old BRW_MAX_GRF limit for the
register allocator (locks the upper limit) and make sure
ptl_register_blocks() always return that amount of blocks (locks
the lower limit).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35781>
2025-07-13 21:11:02 +00:00
Sushma Venkatesh Reddy
172e475705 intel: Add env variable to add break point on/before compute dispatch
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13089
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35353>
2025-07-07 17:43:40 +00:00
Matt Turner
7da88c76db intel: Add support for BFloat16 as cooperative matrix accumulator
The number of passing tests in ./deqp-vk -n '*cooperative_matrix.khr*'
on PTL increases from 914 -> 1030.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35320>
2025-07-02 20:06:59 +00:00
Matt Turner
6842a8179f intel: Add support for float16 as cooperative matrix accumulator
Some checks are pending
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The number of passing tests in ./deqp-vk -n '*cooperative_matrix.khr*'
increases

- on PTL from 787 -> 914
- on RPL from 799 -> 926

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13304
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35616>
2025-06-27 01:26:22 +00:00
Matt Turner
1215845b5b intel: Increase size of cooperative_matrix_configurations[] to 16
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35616>
2025-06-27 01:26:21 +00:00
Caleb Callaway
e7454f5318 intel/debug: shader dump filter
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v2: Fixes filtering for various brw shader dump logic

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35061>
2025-05-23 19:57:02 +00:00
José Roberto de Souza
ddca50584c intel: Return PTL stepping
Without this no temporary workaround is applied to PTL as by
default INTEL_STEPPING_RELEASE is returned and it is larger than
any stepping.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35110>
2025-05-23 13:52:27 +00:00
Jianxun Zhang
ca092db7ce intel/dev: Differentiate displayable PAT entry of compression (xe2)
We need two PAT entries with compression for displayable and
non-displayable compressed images. The current 'compressed' entry
is renamed to 'scanout_compressed' for the displayable.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29928>
2025-05-16 16:03:54 -07:00
José Roberto de Souza
e0a9ec34e7 intel: Add has_partial_mmap_offset to intel_device_info
Commit 3fc79582a1db ("drm/i915: Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps")
increased the I915_PARAM_MMAP_GTT_VERSION version, with that we can
detect what kernel version has the partial mmap fix or not and limit
the usage of this workaround.
This time o mmap will be used in memory pool, so here adding this
propertly to enable or not the feature.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33558>
2025-04-30 12:56:39 +00:00
Tapani Pälli
eeffb4e674 intel/dev: update mesa_defs.json from internal database
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34753>
2025-04-30 11:19:07 +00:00
Caio Oliveira
07fa3b3785 intel: Add support for BFloat16 as cooperative matrix source
Re-organize the configuration lists to make easier to include BFloat16
only for the Gfx125+ that support it, while keeping MTL supporting the
"lowered" configurations from pre-Gfx125.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34105>
2025-04-29 16:29:37 +00:00
Tapani Pälli
765801fd9e intel/dev: add note about PAT entries and Wa_18038669374
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34665>
2025-04-24 09:48:34 +00:00
Lionel Landwerlin
1f6cca0800 intel: fixup a few debugging option checks
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ad328bc58d ("intel: Switch uint64_t intel_debug to a bitset")
Reviewed-by: Michael Cheng <michael.cheng@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34667>
2025-04-23 18:47:42 +00:00
Michael Cheng
3c267535ae anv: Add new debug flag to show shader stage
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Add debug option to show current shader type being
compiled within anv_shader_bin_create.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Casey Bowman <casey.g.bowman@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34596>
2025-04-22 23:09:26 +00:00
Michael Cheng
ad328bc58d intel: Switch uint64_t intel_debug to a bitset
We are reaching our limit of adding flags to intel_debug
(apporaching 64 flags). Switch intel_debug to a bitset,
which gives us almost "unlimited" bits to use in the future.

v2(Michael Cheng): Fixed a few ci errors

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Casey Bowman <casey.g.bowman@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34596>
2025-04-22 23:09:26 +00:00
Michael Cheng
2a1aa129ed intel: Switch debug flags to enums to prep for bitset conversion
Refactored the existing debug flags to use an enum instead of
hardcoded 1ull << N macros. This is a prep step before the
eventual switch of intel_debug to a bitset.

Using enums gives us cleaner indexing and avoids annoying shift
overflow warnings. No functional changes yet.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Casey Bowman <casey.g.bowman@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34596>
2025-04-22 23:09:26 +00:00
Caio Oliveira
050acb9def intel: Disable has_bfloat16 for MTL
Not supported.  Some operations *do* work, but proper support
was removed since it also doesn't support DPAS.

Fixes: 9916cc1050 ("brw: Add BRW_TYPE_BF for bfloat16")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34506>
2025-04-14 18:23:43 +00:00
Caio Oliveira
adfab666a4 intel: Add intel_device_info::has_systolic
Gfx125+ has systolic, with exception for MTL and some ARL
variants.  Update code and tests to use it.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34506>
2025-04-14 18:23:43 +00:00
Lionel Landwerlin
bcaf08b47c intel/dev: remove ADLN references
Not used anymore, just use the existing ADL definitions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34433>
2025-04-11 13:54:35 +00:00
Paulo Zanoni
3db8931d4a intel/i915: restrict the RAM size restrictions to Anv
Before commit b571ae6e7a ("intel: Make memory heaps consistent
between KMDs"), we had the following policy for reporting Sytem RAM
memory sizes:

- For OpenGL, we reported the total available RAM.
- For Vulkan, we reported the total available RAM as:
  - 50% of the total RAM if the total RAM was <= 4GB,
  - 75% otherwise
  - In addition, the Memory Budget (for VK_EXT_memory_budget) is 90%
    of the "free" memory, which can be an extra 10% off of the 50% or
    75%.

When xe.ko was added, one key difference was noted: while i915.ko
reported the "real" RAM memory sizes in its ioctls, xe.ko reported
only 50% of the system RAM as available. Because of that (and other
reasons, see this discussion on MR 28513), commit b571ae6e7a decided
to unify the behavior by changing the Anv i915.ko rule to "always 50%"
instead of "50% or 75%". This also changed the Iris rule to 50%
instead of 100%.

In my research, I couldn't find any reason why this restriction should
also apply to Iris, so here we revert back to handling these size
restrictions on Anv only.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28513>
2025-04-09 22:48:18 +00:00
Tapani Pälli
0750c4c5f1 intel/dev: update mesa_defs.json from internal database
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34430>
2025-04-09 15:44:22 +00:00
Felix DeGrood
a09ddc3b77 anv: add INTEL_DEBUG=shaders-lineno
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30142>
2025-04-08 19:39:53 +00:00
Jordan Justen
f73132f121 intel/dev: Ignore hwconfig difference due to WA 18040209780
Some checks are pending
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Apparently hwconfig has not implemented this workaround.

This warning was noted on MTL and ADL.

> INTEL_HWCONFIG_TOTAL_GS_THREADS (336) != devinfo->max_gs_threads (312)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34243>
2025-03-27 14:52:59 -07:00
Jordan Justen
cdf95273e1 tools/intel_dev_info: Print hwconfig discrepancies
Previously we were printing this information whenever the driver
started, but that proved to noisy.

For example, if running thousands of tests, this would cause thousands
of warnings messages to be printed. (Assuming the driver was built in
debug mode.)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34243>
2025-03-27 14:52:54 -07:00
Jordan Justen
bc86fd5b1f intel/dev: Stop checking hwconfig values at driver runtime
We will move this check into the `intel_dev_info` tool. Unfortunately,
this means we will be much less likely to notice inconsistencies, but
the current strategy has proven to be far too noisy.

For example, if the driver was built in debug mode, then when test
suites are running thousands of tests, the current approach can lead
to thousands of messages being printed.

Closes: mesa/mesa#12141
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34243>
2025-03-27 14:52:49 -07:00