Commit graph

18252 commits

Author SHA1 Message Date
Valentine Burley
fbb42abb9b radv/ci: Add an ASan RADV job on Cezanne
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36348>
2025-08-05 15:07:40 +00:00
Valentine Burley
b3aa602cd5 radv/ci: Use same deqp-runner suite for all RADV jobs
The only difference was the renderer check, which only needs to confirm
"RADV".

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36348>
2025-08-05 15:07:40 +00:00
Samuel Pitoiset
07fe297a3e vulkan: fix missing presentId2/presentWait2 enable features
Fixes recent VKCTS changes for dEQP-VK.info.device_mandatory_features.

Fixes: 07881b085e ("vulkan: Enable PresentWait2 on many physical devices")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36547>
2025-08-05 08:06:43 +00:00
Samuel Pitoiset
72cf81df54 radv: fix fbfetch output with compresed FMASK on <= GFX9
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
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GFX9 might not have DCC but compressed FMASK. In this case, it needs
to be decompressed to handle feedback loops.

Fixes new VKCTS coverage dEQP-VK.dynamic_rendering.*_ms.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36550>
2025-08-05 07:49:31 +00:00
Pavel Asyutchenko
f4cd962434 radv: report full sparse address space size
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13588
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36423>
2025-08-05 07:23:56 +00:00
Rhys Perry
76c96bf558 aco: fix possible scratch offset overflow
We split vector load/store, so consider that we might add to the constant
offset.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36406>
2025-08-04 15:06:44 +00:00
Rhys Perry
44ab4ad732 aco: align scratch size after isel
Make it safe for VGPR spilling if it's not a multiple of 4.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36406>
2025-08-04 15:06:43 +00:00
Rhys Perry
ab10604924 aco/gfx12: fix printing of temporal hints
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36406>
2025-08-04 15:06:41 +00:00
Samuel Pitoiset
5062f6196f radv: replace DGC before/after dispatch helpers with the new ones
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
2025-08-04 11:05:46 +00:00
Samuel Pitoiset
8c37fbd531 radv: add radv_{before,after}_dispatch() functions
Similar to graphics.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
2025-08-04 11:05:46 +00:00
Samuel Pitoiset
23e6494148 radv: handle compute/rt prefetch like graphics
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
2025-08-04 11:05:46 +00:00
Samuel Pitoiset
b7e5bda3e2 radv: rework graphics shaders/vbos prefetch sligthly
To add compute/rt support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
2025-08-04 11:05:46 +00:00
Samuel Pitoiset
23bc1cac86 radv: stop passing compute shader to radv_dispatch()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
2025-08-04 11:05:45 +00:00
Samuel Pitoiset
40ceece75f radv: invalidate compute/rt descriptors at pipeline bind time
No need to delay this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36355>
2025-08-04 11:05:45 +00:00
Eric Engestrom
9ea55d12f6 ci: uprev vkd3d to fix some nvk tests
6be7810766...f0a3820468

The last commit fixes a vkd3d behaviour that's out of spec but is known to work
on AMD hardware to only do that on AMD, thereby fixing at least NVK.

Unfortunately, this also brings a bunch of new failures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36504>
2025-08-04 10:35:11 +00:00
Ritesh Raj Sarraf
717adb6a01 radv/ci: Update flakes uncovered during testing
These new/known flakes were uncovered during testing with Linux 6.16

Signed-off-by: Ritesh Raj Sarraf <ritesh.sarraf@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36493>
2025-08-04 09:57:09 +00:00
Rhys Perry
cec845079e ac/nir/lower_ps: remove barrier for end_invocation_interlock
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
SPIR-V->NIR now inserts this barrier itself.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36513>
2025-08-04 09:30:06 +00:00
Konstantin Seurer
596ee84f16 radv: Use vk_acceleration_struct_vtx_format_supported
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36441>
2025-08-04 08:43:07 +00:00
Emma Anholt
61bf050bb9 ci/radeonsi: Add a flake on mendocino that appeared yesterday.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36496>
2025-08-03 20:27:39 +00:00
Daniel Schürmann
4ca3cc5a1a aco/ra: propagate precolor affinities through parallelcopies and tied definitions
Totals from 214 (0.27% of 79839) affected shaders: (Navi48)

Instrs: 65339 -> 65311 (-0.04%); split: -0.05%, +0.00%
CodeSize: 352616 -> 350952 (-0.47%); split: -0.55%, +0.07%
VGPRs: 9984 -> 9960 (-0.24%)
Latency: 207556 -> 207508 (-0.02%); split: -0.03%, +0.01%
InvThroughput: 40422 -> 40397 (-0.06%)
Copies: 3180 -> 3155 (-0.79%)
VALU: 38347 -> 38322 (-0.07%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
a667d9a68d aco/ra: propagate precolor affinities through phis
Totals from 917 (1.15% of 79839) affected shaders: (Navi48)

Instrs: 3217861 -> 3216947 (-0.03%); split: -0.04%, +0.01%
CodeSize: 17427204 -> 17432264 (+0.03%); split: -0.06%, +0.09%
VGPRs: 65328 -> 65316 (-0.02%)
Latency: 35336268 -> 35335528 (-0.00%); split: -0.01%, +0.01%
InvThroughput: 7305032 -> 7302187 (-0.04%); split: -0.04%, +0.00%
SClause: 120537 -> 120553 (+0.01%); split: -0.01%, +0.02%
Copies: 307257 -> 306852 (-0.13%); split: -0.21%, +0.08%
Branches: 115744 -> 115743 (-0.00%)
VALU: 1572522 -> 1572183 (-0.02%); split: -0.02%, +0.00%
SALU: 574229 -> 574155 (-0.01%); split: -0.05%, +0.04%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
2ddd8ef0a3 aco/ra: don't optimize encodings on precolor affinity mismatch
Totals from 238 (0.30% of 79839) affected shaders: (Navi48)
Instrs: 137836 -> 137176 (-0.48%); split: -0.50%, +0.02%
CodeSize: 728616 -> 728668 (+0.01%); split: -0.06%, +0.07%
Latency: 1503248 -> 1500202 (-0.20%); split: -0.56%, +0.36%
InvThroughput: 297725 -> 296715 (-0.34%); split: -0.70%, +0.36%
Copies: 9390 -> 8825 (-6.02%); split: -6.33%, +0.31%
VALU: 89861 -> 89296 (-0.63%); split: -0.66%, +0.03%
SALU: 13166 -> 13167 (+0.01%); split: -0.05%, +0.06%

Suggested-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
93606a19c6 aco/ra: collect register affinities for all precolored operands.
Totals from 1280 (1.60% of 79839) affected shaders: (Navi48)

Instrs: 817363 -> 812639 (-0.58%); split: -0.58%, +0.00%
CodeSize: 4262644 -> 4243540 (-0.45%); split: -0.45%, +0.00%
VGPRs: 61692 -> 61668 (-0.04%)
Latency: 4354318 -> 4347818 (-0.15%); split: -0.15%, +0.00%
InvThroughput: 711914 -> 707698 (-0.59%); split: -0.59%, +0.00%
VClause: 14685 -> 14677 (-0.05%); split: -0.09%, +0.03%
SClause: 25623 -> 25621 (-0.01%)
Copies: 50663 -> 46242 (-8.73%); split: -8.73%, +0.00%
VALU: 427744 -> 423323 (-1.03%); split: -1.03%, +0.00%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
e32eec52f0 aco/ra: generalize register affinities
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
caa2c22d8b aco/tests: Fix p_startpgm definitions to registers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Alyssa Rosenzweig
82ae8b1d33 treewide: simplify nir_def_rewrite_uses_after
Most of the time with nir_def_rewrite_uses_after, you want to rewrite after the
replacement. Make that the default thing to be more ergonomic and to drop
parent_instr uses.

We leave nir_def_rewrite_uses_after_instr defined if you really want the old
signature with an arbitrary after point.

Via Coccinelle patch:

    @@
    expression a, b;
    @@

    -nir_def_rewrite_uses_after(a, b, b->parent_instr)
    +nir_def_rewrite_uses_after_def(a, b)

Followed by a bunch of sed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
2025-08-01 15:34:24 +00:00
Alyssa Rosenzweig
cc6e3b84cb treewide: use nir_def_as_*
Via Coccinelle patch:

    @@
    expression definition;
    @@

    -nir_instr_as_alu(definition->parent_instr)
    +nir_def_as_alu(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_intrinsic(definition->parent_instr)
    +nir_def_as_intrinsic(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_phi(definition->parent_instr)
    +nir_def_as_phi(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_load_const(definition->parent_instr)
    +nir_def_as_load_const(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_deref(definition->parent_instr)
    +nir_def_as_deref(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_tex(definition->parent_instr)
    +nir_def_as_tex(definition)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
2025-08-01 15:34:24 +00:00
Martin Roukala (né Peres)
eab24d7793 radv/ci: document new flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36439>
2025-08-01 09:42:03 +03:00
Eric Engestrom
15d554592b radv/ci: add missing GPU_VERSION for navi10 in kws farm
Fixes: d40438031c ("radv/ci: deduplicate GPU_VERSION in ci-tron jobs")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36499>
2025-07-31 21:50:12 +00:00
Collabora's Gfx CI Team
f99a60f499 Uprev Piglit to c3a3e29d59e0972650a6d30d20de930c87739c14
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
0980079dcf...c3a3e29d59

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36340>
2025-07-31 21:05:20 +00:00
Antonio Ospite
ddf2aa3a4d build: avoid redefining unreachable() which is standard in C23
In the C23 standard unreachable() is now a predefined function-like
macro in <stddef.h>

See https://android.googlesource.com/platform/bionic/+/HEAD/docs/c23.md#is-now-a-predefined-function_like-macro-in

And this causes build errors when building for C23:

-----------------------------------------------------------------------
In file included from ../src/util/log.h:30,
                 from ../src/util/log.c:30:
../src/util/macros.h:123:9: warning: "unreachable" redefined
  123 | #define unreachable(str)    \
      |         ^~~~~~~~~~~
In file included from ../src/util/macros.h:31:
/usr/lib/gcc/x86_64-linux-gnu/14/include/stddef.h:456:9: note: this is the location of the previous definition
  456 | #define unreachable() (__builtin_unreachable ())
      |         ^~~~~~~~~~~
-----------------------------------------------------------------------

So don't redefine it with the same name, but use the name UNREACHABLE()
to also signify it's a macro.

Using a different name also makes sense because the behavior of the
macro was extending the one of __builtin_unreachable() anyway, and it
also had a different signature, accepting one argument, compared to the
standard unreachable() with no arguments.

This change improves the chances of building mesa with the C23 standard,
which for instance is the default in recent AOSP versions.

All the instances of the macro, including the definition, were updated
with the following command line:

  git grep -l '[^_]unreachable(' -- "src/**" | sort | uniq | \
  while read file; \
  do \
    sed -e 's/\([^_]\)unreachable(/\1UNREACHABLE(/g' -i "$file"; \
  done && \
  sed -e 's/#undef unreachable/#undef UNREACHABLE/g' -i src/intel/isl/isl_aux_info.c

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36437>
2025-07-31 17:49:42 +00:00
Georg Lehmann
a6a6c2f691 aco/ra: convert bitwise instruction to gfx11+ 16bit on demand
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
The 32bit versions are smaller, allow more optimizations and VOPD,
so only use the 16bit opcodes if nessecary.

Foz-DB Navi31:
Totals from 84 (0.10% of 80237) affected shaders:
Instrs: 176673 -> 176347 (-0.18%); split: -0.20%, +0.01%
CodeSize: 970148 -> 969716 (-0.04%); split: -0.08%, +0.03%
VGPRs: 5876 -> 5864 (-0.20%)
Latency: 2805974 -> 2805674 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 769007 -> 768738 (-0.03%); split: -0.04%, +0.01%
VClause: 2593 -> 2597 (+0.15%)
Copies: 23749 -> 23487 (-1.10%); split: -1.11%, +0.00%
VALU: 107124 -> 106862 (-0.24%); split: -0.25%, +0.00%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35919>
2025-07-31 12:07:07 +00:00
Georg Lehmann
404e1f13e8 aco/print_asm: use real true16 instr on gfx11+
Fake16 doesn't print opsel on v_cndmask_b16, so it looks really broken.
Restrict to LLVM20+ because older versions have incomplete tru16 support.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35919>
2025-07-31 12:07:07 +00:00
Eric Engestrom
d40438031c radv/ci: deduplicate GPU_VERSION in ci-tron jobs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36354>
2025-07-30 23:18:04 +00:00
Eric Engestrom
84ca8c54f7 radv/ci: deduplicate DEQP_SUITE: radv-valve in ci-tron jobs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36354>
2025-07-30 23:18:03 +00:00
Georg Lehmann
4683187f49 radv/nir/lower_cmat: load gfx11 8bit ACC using the B layout to get aligned loads
This allows us to use aligned loads that can be vectorized, without any
downside as 8bit scalar loads always write 16bits of a register.

Foz-DB Navi31:
Totals from 10 out of 14 FSR4 shader:
MaxWaves: 71 -> 68 (-4.23%)
Instrs: 60146 -> 59781 (-0.61%); split: -0.67%, +0.06%
CodeSize: 412448 -> 413428 (+0.24%); split: -0.11%, +0.35%
VGPRs: 2112 -> 2160 (+2.27%)
SpillVGPRs: 89 -> 68 (-23.60%)
Scratch: 11776 -> 8704 (-26.09%)
Latency: 196628 -> 193770 (-1.45%); split: -2.62%, +1.17%
InvThroughput: 224944 -> 226274 (+0.59%); split: -0.02%, +0.61%
VClause: 862 -> 796 (-7.66%)
Copies: 3166 -> 3342 (+5.56%); split: -6.22%, +11.78%
Branches: 37 -> 38 (+2.70%)
PreSGPRs: 311 -> 312 (+0.32%)
PreVGPRs: 2153 -> 2214 (+2.83%); split: -1.35%, +4.18%
VALU: 51073 -> 51448 (+0.73%); split: -0.03%, +0.77%
SALU: 1072 -> 1074 (+0.19%)
VMEM: 3275 -> 2765 (-15.57%)
VOPD: 1739 -> 1783 (+2.53%); split: +7.99%, -5.46%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36117>
2025-07-30 07:25:51 +00:00
Marek Olšák
8d3e76c250 nir: split nir_move_load_frag_coord from nir_move_load_input
It's a pure system value on AMD, not an input.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36357>
2025-07-29 16:20:48 -04:00
Antonio Ospite
0dd8051f34 radv: fix returning _Bool instead of pointer
When building for C23 the compiler warns about returning a boolean when
a different type is expected instead.

Change the code to return NULL instead of false, fixing the following
errors:

-----------------------------------------------------------------------
../src/amd/vulkan/radv_pipeline_cache.c: In function ‘radv_pipeline_cache_object_search’:
../src/amd/vulkan/radv_pipeline_cache.c:338:14: error: incompatible types when returning type ‘_Bool’ but ‘struct radv_pipeline_cache_object *’ was expected
  338 |       return false;
      |              ^~~~~
../src/amd/vulkan/radv_pipeline_cache.c:352:14: error: incompatible types when returning type ‘_Bool’ but ‘struct radv_pipeline_cache_object *’ was expected
  352 |       return false;
      |              ^~~~~
-----------------------------------------------------------------------

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36323>
2025-07-29 14:07:06 +00:00
llyyr
c869971d05 radv: don't set HOST_IMAGE_TRANSFER_BIT if host_image_copy not enabled
This can't work if the extension isn't enabled, so only set if the
extension is enabled.

Fixes: d89b11011f ("radv: add support for formats with host-transfer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36400>
2025-07-29 13:48:59 +00:00
Nagulendran, Iswara
6088dbe05c amd/vpelib: Fix cost profiling support
Add additional changes/logs to profile total register writes.

Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:25 +00:00
Chang, Tomson
02beb30d6b amd/vpelib: Update register header and definitions macros
Update header and related macros and functions

Reviewed-by: Min-Hsuan You <Min-Hsuan.You@amd.com>
Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:25 +00:00
Chan, Roy
08fd9aab30 amd/vpelib: fix memory corruption
[WHY]
Wrong structure size being allocated

[HOW]
fixed the structure size during allocation

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:25 +00:00
Nagulendran, Iswara
74c88f740f amd/vpelib: Fix Issues with Background Color insertions
[WHY]
Background Color Insertion, test cases involving studio output fails

[HOW]
Move background color convertion into revision specific resource
files and isolated what needed to be executed for VPE

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:25 +00:00
Assadian, Navid
b529d38ae9 amd/vpelib: Exit when VPE not support in debug
When the debug flag is set to assert when vpe is not supported, instead
of assert it is preferable to exit so the CI aborts the process instead
of waiting on the assert message.

[WHY]
In debug mode for CI, when assert the process doesn't abort and the CI
terminates on time out.

[HOW]
Using exit instead of assert

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:24 +00:00
Kovac, Krunoslav
5b8b5c4c49 amd/vpelib: Fix Possible dereferencing null
pointer issue

[WHY]
Mostly dereferencing possible null ptrs

[HOW]
Add checks / refactor code.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:24 +00:00
Chang, Tomson
48495c142a amd/vpelib: Add missing swizzle and dcc info
Add missing swizzle mode and dcc info

Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Reviewed-by: Jude Shih <Jude.Shih@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:24 +00:00
Hsieh, Mike
d281a5587d amd/vpelib: add max/min input output capability
[WHY]
Capability need to show max and min input/output size.

[HOW]
Add max_input_size, max_ouptut_size, min_output_size and min_imput_size.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Ricky Lin <Ricky.Lin@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:24 +00:00
Hsieh, Mike
6b279abcac amd/vpelib: bug fix: remove unnecessary free
[WHY]
vpe_priv.resource should not be freed when destroy resource

[HOW]
Remove unnecessary free.

Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Brendan Steve Leder <BrendanSteven.Leder@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:24 +00:00
Hsieh, Mike
e1ff093e63 amd/vpelib: add format, colorspace check function
[WHY]
VPE does not support pixel format and colorspace support check.

[HOW]
add vpe_create_engine function to support stateless API.
Add new function to support pixel format check and colorspace support
check.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:24 +00:00
Agate, Jesse
0541d73cbd amd/vpelib: Use Ceil Division Macro
Use available ceil division macro

[WHY]
Code Cleanup

[HOW]
Use available macro

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
2025-07-29 09:17:24 +00:00