Commit graph

177366 commits

Author SHA1 Message Date
Alyssa Rosenzweig
f6df092925 agx: Annotate opcodes with a scheduling class
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
6f189afcd5 agx/validate: Print to stderr
Otherwise unusable.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
0df6f22bd1 agx: Fix jmp_exec_none encoding
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Alyssa Rosenzweig
a58bb49fc0 asahi: Fixes for clang-warnings
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Christian Gmeiner
c2b803090b agx/lower_address: Remove not used has_offset
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Christian Gmeiner
d97a79a85e agx/lower_address: Use intrinsics_pass
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:34 +00:00
Neal Gompa
251008c1bf asahi: Fix 32-bit x86 build with correct data type for overflow error message
Currently, when building on 32-bit x86, we get compilation errors
due to data type mis-matches in the format string.

This should fix the issue.

Signed-off-by: Neal Gompa <neal@gompa.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
cce1933ca5 rusticl: enable asahi
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
b70172baff rusticl/memory: fallback if allocating linear images fails
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
7fd3e53279 asahi: handle images in is_format_supported
Some frontends differentiate between textures and images more explicitly
than st/mesa. So we might end up with PIPE_BIND_SHADER_IMAGE but not
PIPE_BIND_SAMPLER_VIEW in is_format_supported.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
3bc09aaf1a asahi: gracefully handle allocating linear images
Frontends might try to allocate linear textures or images, we  should
gracefully return NULL so frontends can do fallback paths.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
01aa487c40 asahi: implement clear_buffer
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
91f4062959 asahi: implement set_global_binding
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
9b59602338 asahi: implement get_compute_state_info
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
9f8a466e03 asahi: handle load_global_invocation_id_zero_base
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
ce5d1100eb asahi: handle load_workgroup_size
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
36e42299fa asahi: handle kernels
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
37597c60ea asahi: lower hadd
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Karol Herbst
36235b5668 asahi: fetch available system memory
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
2023-09-05 18:50:33 +00:00
Connor Abbott
1cef1f02b5 vk/graphics_state: Fix copying MS locations pipeline state
Copying the state below overwrote the ms.sample_locations we set,
so our new_sample_locations was never actually used and we were
accidentally doing a shallow copy. Turnip passes a stack-allocated
old_state, so this resulted in invalid stack pointers.

Fixes: f497cc9d56 ("vk/graphics_state: Add helpers for pre-baking state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25031>
2023-09-05 18:09:41 +00:00
Eric Engestrom
7cf13ea504 ci: skip containers & build jobs when disabling a farm
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25032>
2023-09-05 14:04:52 -04:00
Danylo Piliaiev
83cb5c3491 tu/a7xx: Disable LRZ
Even with GMEM disabled LRZ is still interacted with in some cases.
So it has to be completely disabled until it is fixed.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
4b84ae157a tu/a7xx: Fix CmdDrawIndirectByteCountEXT
On a7xx DI_SRC_SEL_AUTO_INDEX is used instead of DI_SRC_SEL_AUTO_XFB.

On a7xx the counter value and offset are shifted right by 2, so
the vertexStride should also be in units of dwords.
CTS doesn't test this though.

Fixes:
 dEQP-VK.transform_feedback.simple.draw_indirect_*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
a2191239f9 tu/a7xx: Fix 3d blits after multiview usage
Fixes cts tests:
 dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
720480943d tu/a7xx: Fix occlusion query
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Mark Collins
9eaf8ab8a0 tu/a7xx: Adapt r3d blits for A7xx
As r3d_ops emits sysmem draws directly, it needs to be manually
updated to emit the A7XX commands instead of A6XX.

VK-CTS tests success on A630 + A740:
dEQP-VK.api.copy_and_blit.core.blit_image.*

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
cdf28d3b4f tu/a7xx: Fix flat shading
dEQP-VK.rasterization.flatshading.* are passing.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
15334c045e tu/a7xx: Fix multiview
dEQP-VK.multiview.* mostly works, fails seem to be caused by lack of
3d blits.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
d13c5aeee8 tu/a7xx: Fix tesselation shaders
dEQP-VK.tessellation.* are passing now.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
d9b33245d4 tu/a7xx: Fix geometry shaders
dEQP-VK.geometry.* are passing now

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
4dc75fc723 freedreno/fdl: Set LOSSLESSCOMPEN for image when ubwc is enabled on a7xx
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
95104707f1 tu: Basic a7xx support
Works:
- sysmem rendering

Doesn't work:
- gmem rendering
- 3d blits
- TESS and GS

Wild Life Extreme benchmarks runs without issues, most Sascha Willems
Vulkan demos are working.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
e19272a7a2 tu/common: Generalize TU_GENX macro
Now it doesn't require generated macro.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
7a01325200 ir3/a7xx: Disable shared consts for a7xx
a7xx introduced a new way to upload shared consts with old one
becoming unavailable, use fallback mechanism until we implement
the new shared consts.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
ba32f44da9 ir3/a7xx: Use ccinv for data synchronization
Fixes a lot of tests in dEQP-VK.memory_model.* e.g.:
 dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_local.buffer.comp

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
99457286c9 ir3/a7xx: Add ccinv instruction
_Presumably_ invalidates workgroup-wide cache for image/buffer data access.
so while "fence" is enough to synchronize data access inside a workgroup,
for cross-workgroup synchronization we have to invalidate that cache.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:30 +00:00
Danylo Piliaiev
9b7452c5e6 ir3/a7xx: insert lock/unlock at the end of every compute shader
Add (ss)(sy) in all cases until.

TODO: Set sync flags depending on real need.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
5f89ce8799 ir3/a7xx: Don't multiply global mem instruction's offset by 4
a7xx global memory instructions don't have implied shift.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
5d0d5108d7 ir3/a7xx: cat5 mode1 has swapped tex/samp ids
Though blob is not seen to even use mode1 on a740, it uses
S2EN variant instead.

Fixes:
 dEQP-VK.binding_model.descriptor_buffer.multiple.*
 dEQP-VK.binding_model.descriptor_buffer.embedded_imm_samplers.*
 dEQP-VK.pipeline.monolithic.descriptor_limits.compute_shader.*

Adapted from Jonathan Marek's changes.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
d0ab1a6217 isaspec: Make possible to obtain gpu_id in <expr> blocks
Done with ISA_GPU_ID() macro. This makes possible to use
gpu generation in to select between overrides.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
7e10a175c7 freedreno/computerator: Fix remaining issues with A7XX
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
b0ea4883f0 ir3/tests: Use fd_dev_info to infer GPU generation
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
cd3719be7d freedreno: Fully define a730 and a740 device properties
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
a70e04b0c0 freedreno: Add a list of raw magic regs
The set of magic regs is different between generations and even
sub-gens. Adding a new one and/or emitting one on specific generation
takes much more code than necessary. Doing this in a single place is
much nicer.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
0b25388afe freedreno/registers: Generate python files with reg offsets
This would allow us to use register names in python scripts.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Danylo Piliaiev
a9fc9bc46b freedreno/registers: Refactor gen_header.py to allow more options
We want it to also generate .py files with reg definitions.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
2023-09-05 16:19:29 +00:00
Lionel Landwerlin
10e75aae1b intel/nir: rerun lower_tex if it lowers something
nir_lower_tex can lower tg4 coords into tg4 offset which on DG2+ we
also need to lower into constant offsets.

Unfortunately the nir_lower_tex pass is not able to lower the
instructions it itself generates, so the easy fix for when
nir_lower_tex lowers tg4 coords into tg4 offsets is to rerun the pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9735
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25015>
2023-09-05 13:35:51 +00:00
Vlad Schiller
c4506b5af5 pvr: Implement VK_KHR_format_feature_flags2
This commit will implement and set VK_KHR_format_feature_flags2
instead of the old ones.

Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24929>
2023-09-05 13:15:30 +00:00
Samuel Pitoiset
e80fddf81f radv/amdgpu: do not copy the original chain link for IBs
Otherwise, if a secondary CS is grown and then executed without IB2,
the INDIRECT_BUFFER packet would have been copied but it shouldn't.

This fixes a regression that introduced GPU hangs with
gl_vk_meshlet_cadscene on RDNA2.

Fixes: df0c742543 ("radv/amdgpu: rework growing a CS with the chained IB path slightly")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
2023-09-05 12:38:33 +00:00
Samuel Pitoiset
9206aeb077 radv/amdgpu: fix executing secondaries without IB2
If a secondary cmdbuf has been grown and is executed without IB2
(eg. on compute queue or when it's not allowed), the ib size ptr
contains chaining info, which means the IB size was wrong.

This fixes CPU crashes when running gl_vk_meshlet_cadscene.

Fixes: 277b2afd70 ("radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
2023-09-05 12:38:33 +00:00