Commit graph

131553 commits

Author SHA1 Message Date
Boris Brezillon
f0a767f0e4 nir: Fix LOD source type for txf_ms instructions
txf_ms takes an integer LOD, not a float.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
2020-11-25 16:21:10 +01:00
Rhys Perry
4eac442217 aco/ngg: fix division-by-zero in assertion
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
2020-11-25 13:41:04 +00:00
Rhys Perry
37a2c9ace6 aco: fix GS with no outputs
With NGG, ngg_gs_known_vtxcnt[0] would be false and ngg_gs_finale() would
assert.

With legacy GS, I don't know why the assertion was there.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
2020-11-25 13:41:04 +00:00
Rhys Perry
fdfa96561e radv/llvm,aco/ngg: fix large shift exponent in ngg_gs_vertex_lds_addr
When vertices_out=0, we will try to shift 1u by UINT32_MAX.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
2020-11-25 13:41:04 +00:00
Alyssa Rosenzweig
d299c2eb0b pan/bi: Implement shader-db stats
v2: Drop register tracking since it was wrong, and meaningful accounting
is tricky for Bifrost (which wants round robin RA for at least some
registers)... we'll cross that bridge when we get there, possibly
preferring a "max liveness" estimate to the raw RA output.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Alyssa Rosenzweig
45de02bdac pan/bi: Ensure TEXC src0 is not marked SSA
Prevents attempts to spill tied TEXC src/dest, resulting in a crash,
seen in shaders/tesseract/229.shader_test

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Boris Brezillon
bbd3a8eadd pan/bi: Emit a combine even if we only pass one staging reg to TEXC
We need that to account for potential swizzling on the source reg.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Alyssa Rosenzweig
b9121624fc pan/bi: Fix off-by-one in RA
Could result in trying to allocate R64 which is clearly wrong.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Alyssa Rosenzweig
087e3f8da8 pan/bi: Fix varying writemask handling
Allows shaders/supertuxkart/1.shader_test and
shaders/unity/24-Tree.shader_test to compile.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Alyssa Rosenzweig
eee2a43461 pan/bi: Implement sampler1D
Enough to get shaders/humus-celshading/1.shader_test compiling, no idea
if it actually works but it looks reasonable.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Alyssa Rosenzweig
8b23fbb954 pan/mdg: Fix shader-db counter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Alyssa Rosenzweig
028de3beaf panfrost: Enable indirect uniform indexing
It works fine, and without it, the lowering bloats GLES2 shaders (by a
factor of 20x for one shader on t-rex!)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Alyssa Rosenzweig
33a7645542 panfrost: Add PAN_GPU_ID debug option
I'd like to run shader-db locally without turning on the Bifrost
machine. I'm lazy, it's just for debug builds, ok? 😇

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
2020-11-25 13:15:05 +00:00
Rhys Perry
2a1238f3a3 nir/unsigned_upper_bound: decrement num_sources_left before recursing
Otherwise, search_phi_bcsel() will be called with a buf_size that is
slightly lower than it has to be.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7748>
2020-11-25 11:26:42 +00:00
Rhys Perry
65fbae16e3 nir/unsigned_upper_bound: fix buffer overflow in search_phi_bcsel
It should only recurse if there's enough space to add the phi sources.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 72ac3f6026 ("nir: add nir_unsigned_upper_bound and nir_addition_might_overflow")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7748>
2020-11-25 11:26:42 +00:00
Rhys Perry
cf0b54cdc1 aco: fix v_mul_hi_u32_u24 format
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 57c152af9c ("aco: select v_mul_{hi}_u32_u24 for 24-bit multiplications")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3874
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7759>
2020-11-25 10:59:44 +00:00
Erik Faye-Lund
ecebc263f5 Revert "util: Add helpers for various one-time-init patters"
This reverts commit bda4d6e0d0.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
86662655ec Revert "nir: Use get_once() helper for one-time init's"
This reverts commit c9062df1d5.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
5461e21245 Revert "freedreno/ir3: Use get_once() for one-time init"
This reverts commit b4ad27a986.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
b8fb95ce01 Revert "gallium/hud: Use do_once for one-time init"
This reverts commit 2e81ec5e00.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
f20192f7c3 Revert "mesa/st: Use do_once for one-time init"
This reverts commit bcb2981e14.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
410b651859 Revert "util: Fix helgrind complaint about one-time init"
This reverts commit f8c7a43f33.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
8fffcbce9b Revert "mesa: Fix helgrind complaint about one-time init"
This reverts commit f7102ac376.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
1f6e03c3bf Revert "gallium/trace: Fix helgrind complaint about one-time init"
This reverts commit 1aa055539f.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Erik Faye-Lund
f57f040f13 Revert "tgsi: Fix helgrind complaint about one-time init"
This reverts commit d91fe7d1c6.

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
2020-11-25 09:44:11 +00:00
Samuel Pitoiset
8da98beb5d radv: always use 32-bit predication on compute queues
It seems that only gfx queue doesn't support it, except on GFX10.3
which supports all queues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
2020-11-25 08:13:43 +00:00
Samuel Pitoiset
62d9ca696e radv: use 32-bit predication for conditional rendering on GFX10.3+
It's now supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
2020-11-25 08:13:43 +00:00
Samuel Pitoiset
b1558ec3ec ac: add gpu_info::has_32bit_predication
32-bit predication is now supported with GFX10.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
2020-11-25 08:13:43 +00:00
Ella-0
472e81ed80 v3dv: Wayland WSI support
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7303>
2020-11-25 07:49:53 +01:00
Jason Ekstrand
9fa1cdfe7f intel/rt: Implement push constants as global memory reads
They're not really "push" anymore but that's because there is no such
thing as push constants in bindless shaders on Intel.  They should be
fast enough, though.  There is some room for debate here as to whether
we want to do the pull in NIR or push it into the back-end.  The
advantage of doing it in the back-end is that it'd be easier to use
MOV_INDIRECT for indirect push constant access rather than falling back
to a dataport message.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
f7e24e559f intel/rt: Add support for hit attributes
For triangle geometry, the hit attributes are always two floats which
contain the barycentric coordinates of the hit.  For procedural
geometry, they're an arbitrary blob of data passed from the intersection
shader to the hit shaders.  In our implementation, we stash that data
right after the HW RayQuery in the ray stack.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
96fde5518b intel/rt: Add a helper to create the raygen trampoline shader
Unlike graphics and compute pipelines, Vulkan ray-tracing pipelines do
not have a single entrypoint.  Instead, the raygen shader is specified
as a one-element shader binding table in the vkCmdTraceRay call.  This
means that raygen shaders have to be bindless shaders just like any
other ray tracing shader.  To launch them, we have a tiny compute shader
that acts as a trampoline and sets up the hotzone and uses btd_spawn to
fire off the raygen shader.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
303378e1dd intel/rt: Add lowering for combined intersection/any-hit shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
cb261b03e5 intel/rt: Add lowering for ray-walk intrinsics in any-hit shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
c3ddefa000 intel/rt: Add support for shader buffer record memory
Most of the work for this is done for us by spirv_to_nir which gives us
a load_global from a memory address based on the shader_record_ptr
system values.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
9ba7d459a3 intel/rt: Implement the new ray-tracing system values
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
7ce7c93755 intel/rt: Implement traceRay()
This is a little bit more work than executeCallable() because we also
have to set up the MemRay data structure which the ray traversal
hardware uses to keep its state.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
75209d5bd1 intel/fs: Add and implement intel-specific ray-tracing intrinsics
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
1f6ae809ef intel/rt: Implement support for shader call payloads
Both traceRay() and executeCallable() take a payload parameter which
gets passed from the caller to the callee and which the callee can write
to pass data back to the caller.  We implement these by passing a
pointer to the data structure in the callee to the caller as the second
QWord on its stack.  Coming out of spirv_to_nir, the incoming call
payloads get the nir_var_shader_call_data variable mode allowing us to
easily identify them.  Outgoing call payloads get assigned the
nir_var_shader_temp mode and will have been turned into function_temp by
nir_lower_global_vars_to_local.  All we have to do is crawl the shader
looking for references to the nir_var_shader_call_data variable and
rewrite those to use the passed in pointer.  nir_lower_explicit_io will
do the rest for us.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
72354b0e9d intel/rt: Add a helper to create a trivial return shader
These are required for ray-tracing.  There are many cases where the
ray-tracing hardware may decide to execute some but not all of our
shaders.  In these cases, it needs a shader to execute at the end which
will pop the stack back to the shader which called traceRay().

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
fad81a3968 intel/rt: Add a pass to lower shader call instructions
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
ca88cd8e5a intel/rt: Add return instructions at the end of ray-tracing shaders
Each callable ray-tracing shader shader stage has to perform a return
operation at the end.  In the case of raygen shaders, it retires the
bindless thread because the raygen shader is always the root of the call
tree.  In the case of any-hit shaders, the default action is accep the
hit.  For callable, miss, and closest-hit shaders, it does a return
operation.  The assumption is that the calling shader has placed a
BINDLESS_SHADER_RECORD address for the return in the first QWord of the
callee's scratch space.  The return operation simply loads this value
and calls a btd_spawn intrinsic to jump to it.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
49778a7253 intel/rt: Add support for scratch in ray-tracing shaders
In ray-tracing shader stages, we have a real call stack and so we can't
use the normal scratch mechanism.  Instead, the invocation's stack lives
in a memory region of the RT scratch buffer that sits after the HW ray
stacks.  We handle this by asking nir_lower_io to lower local variables
to 64-bit global memory access.  Unlike nir_lower_io for 32-bit offset
scratch, when 64-bit global access is requested, nir_lower_io generates
an address calculation which starts from a load_scratch_base_ptr.  We
then lower this intrinsic to the appropriate address calculation in
brw_nir_lower_rt_intrinsics.

When a COMPUTE_WALKER command is sent to the hardware with the BTD Mode
bit set to true, the hardware generates a set of stack IDs, one for each
invocation.  These then get passed along from one shader invocation to
the next as we trace the ray.  We can use those stack IDs to figure out
which stack our invocation needs to access.  Because we may not be the
first shader in the stack, there's a per-stack offset that gets stored
in the "hotzone".

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
2b3f6cdc6c intel/rt: Add lowering functions for each ray-tracing stage
These will eventually contain per-stage lowering for various ray-tracing
things.  This is separate from brw_nir_lower_rt_intrinsics because, for
reasons that will become apparent later, brw_nir_lower_rt_intrinsics has
to be run very late in the compile process, right before brw_compile_bs.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
c7660918d7 intel/rt: Add a pass to lower the new ray-tracing intrinsics
The new intrinsics we added for doing address calculations are all
things we fetch from the RT_DISPATCH_GLOBALS struct.  We could emit an
RT_DISPATCH_GLOBALS load at every point we want it and trust NIR to CSE
it for us but it's easier to use intermediate intrinsics.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
6e50db4eda intel/rt: Add builder helpers for accessing RT data structures
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:10 +00:00
Jason Ekstrand
1f6e70c85a intel/fs: Add and implement a load_global_const_block intrinsic
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:09 +00:00
Jason Ekstrand
6d5b57aeb7 intel/rt: Add a brw_rt.h header with #defines for basic RT data structures
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:09 +00:00
Jason Ekstrand
7280b0911d intel/compiler: Add support for bindless shaders
The Intel bindless thread dispatch model is very simple.  When a compute
shader is to be used for bindless dispatch, it can request a set of
stack IDs.  These are allocated per-dual-subslice by the hardware and
recycled automatically when the stack ID is returned.  Passed to the
bindless dispatch are a global argument address, a stack ID, and an
address of the BINDLESS_SHADER_RECORD to invoke.  When the bindless
shader is dispatched, it is passed its stack ID as well as the global
and local argument pointers.  The local argument pointer is the address
of the BINDLESS_SHADER_RECORD plus some offset which is specified as
part of the BINDLESS_SHADER_RECORD.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:09 +00:00
Jason Ekstrand
27f44116fe intel/debug: Add a debug flag for ray-tracing shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
2020-11-25 05:37:09 +00:00