- fullsync - adds (ss)(sy) after each cat4/cat5/cat6
- fullnop - adds (rpt4) nop before every instruction
Useful to debug errors in inter-instruction synchronization.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27012>
There was a WAR hazard if something writes to sources last STG is
using. (sy)nop did not wait for sources to become "free", we
need to use (ss).
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27013>
The scratch size gets assigned by nir_lower_vars_to_explicit_types. Now
that we only run it once on temp memory, there is no need to reset the
value.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27068>
The implicit flushing is only required if the resource is shared
and changes to the resource must be visible outside of the screen
after the flush. For non-shared resources we can rely on the
screen internal tracking of data updates.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25756>
Track if resources are shared outside of the screen, which means
changes to the resource must be visible to the external observers
after a flush and the resource might be manipulated by other
agents than the contexts from the screen.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25756>
As driver supports OpenGL 3.1, run proper tests, besides the OpenGL ES
tests.
Note that including GL3.1 is not required to include previous versions.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27069>
d3dkmthk.h contains only non driver specific structs, private
data structs are not defined anywhere public but contain
important information for memory allocation and submissions.
Luckily only small parts of these structs are relevant for what
we want to do and most of them are not changed between calls.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26101>
Move ralloc allocations and frees for BOs into the critical sections
protected with mutexes.
This fixes several double-free and use-after-free crashes that happens
sometimes when using the simulator to run Vulkan CTS tests, specially
when these tests involve multithreading, like
`dEQP-VK.api.object_management.multithreaded_per_thread_resources.device_memory_small`.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27070>
This mirrors the changes in 69ff9c16bb ("radeonsi: never set
DISABLE_WR_CONFIRM for CP DMA clears and copies").
Cc: mesa-stable
Suggested-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27053>
At some point, we will probably have a VK_SHADER_CREATE_xxx flag
matching the pipeline one. So, I think it's more like a per-shader
field. It can also be useful to disable optimisations per stage when
debugging.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
For storing the per-stage key information like robustness etc. This
will fit well with ESO as well.
For pipelines, they are copied from radv_pipeline_key, similarly to
the radv_pipeline_layout/radv_shader_layout pair.
This will also allow us to kill radv_pipeline_key for compute/rt
pipelines.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27007>
Useful if you encounter some kind of pagefault (including with
AUX-TT).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
Gives us the ability to check whether the compute command streamer is
hung.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
When capturing INTEL_DEBUG=capture-all and the application has like
1Gb of vertex data, you might not want to actually decode it when
looking at the error state.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27058>
Vivante hardware handles 64bpp render targets and samplers in a odd way
by splitting the buffer and using a pair of texture samplers or a pair
of MRT outputs to access those resources. This isn't implemented in the
driver right now, so we should not advertise support for those formats.
CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26982>
We are toggling preemption on/off during streamout, this is also
happening on gfx12 platforms, not just dg2.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27002>
Fix defects reported by Coverity Scan.
Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In reg_file = reg_file = brw_inst_dpas_3src_dst_reg_file(devinfo, inst),
reg_file is written twice with the same value.
Fixes: 1c92dad5cb ("intel/disasm: Disassembly support for DPAS")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27056>
Iris driver includes system DRM UAPI header before the Mesa's internal
ones, which makes Iris to use the system headers. Correct the included
header for consistency with the rest of the Intel driver code by changing
the inclusion order, like it's done by the rest of the Intel driver code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27043>
