This also introduces a new tier since the common helper exposes
25% of memory as heap on devices with <=1GiB memory. Previously
50% was being used.
This also fixes `device->heap_used` not using atomic read.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41242>
The budget calculation has changes slightly as the budget scaling
is applied prior to adding the used up heap memory.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41242>
Some drivers scale the available memory proportionally to the
advertised heap memory. The `heap_memory_percent` driconf option
allows tweaking the percentage of system memory exposed as heap
memory, so drivers supporting this also need to scale their
budgets accordingly. So add `vk_gpu_heap_budget_from_system()`.
Some drivers just clamp the available memory to the heap size. This
is accounted for by having the `scale_with_heap` parameter.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41242>
Also adds helper function to be used by drivers.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41242>
When moving the code of creating image views to the init_sampler_view()
function, the check for Z/S aspect bits was forgotten to be added
(because it was a big if gating a lot of code originally).
When the driver doesn't have needs_zs_shader_swizzle set, this is not
problematic, because the condition for creating Z/S view is to have only
Z aspect; however the needs_zs_shader_swizzle case now fails because Z/S
views are now created for color images.
Fix the issue by re-adding the Z/S aspect check before checking
needs_zs_shader_swizzle flag.
Fixes: cafa22142b ("zink: create views for samplers lazily")
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41923>
agx_batch_writes_range takes the offset within the buffer, not the address
Fixes: 4a3b905bb8 ("agx: move texture lowering into lib")
Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41386>
When both inputs are denorms, the bcsel picks the integer min/max result,
which does not flush denorms and therefore might return the wrong result.
Fixes OpenCL fmin/fmax on asahi.
Fixes: d238d766c6 ("nir: add lower_fminmax_signed_zero")
Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41386>
numFds could be no less than 1 based on the number of plane(s) and
metadata(optional) fd in a gralloc buf handle. and amdgpu backend
of gralloc should make sure all plane bufs within same dma_buf fd
but different offset.
handle->data[0] already indicates dma_buf fd of plane(s) well.
Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41879>
This change updates the configuration to fix some
regressions with the fpu64 emulation.
Note: The r600 has a single precision fma op code which
breaks the fpu64 emulation if used as nir_op_ffma (It
likely returns a double).
This change was tested on palm and barts.
Fixes: aeea2e7c1f ("nir: add fmad_or_ffma helpers and use it in lower_double_ops")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41781>
The Mesa PowerVR driver is Vulkan only, and Zink is used solely for
APIs implemented by Gallium.
Change the driver name to "zink" if the device node's driver is
"powervr".
Backport-to: 26.1
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41737>
This reverts commit adf18abb40.
Some setups rely on matching kmsro for render nodes (e.g. clients to
wlroot-based compositors).
Backport-to: 26.1
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41737>
brw_nir_lower_deferred_urb_writes assumes that constant offsets will be
properly folded. In brw itself we call the big optimization loop which
takes care of this, but jay doesn't do that in-between.
At any rate, nir_lower_io generates a lot of address math that really
ought to get cleaned up, so it seems like a good point to call it here.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
I meant to add these together, not put a random semicolon in the middle
of the expression which meant the offset got tossed on the floor.
Fixes: 6fbe201a12 ("brw: Convert VS/TES/GS outputs to URB intrinsics.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
We now calculate it when emitting push input loads at the NIR level,
rather than in the backend.
v2: Fix missing interaction with legacy tesslevel remapping
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
We were seeing if the start of the load was within the push range,
rather than the entire load. (We could also split loads, but that
seems needlessly complex.)
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
Calculate the end of our read as a byte offset and divide by the 32B
unit of URB reads. We were calculating 1 byte beyond the start offset
and dividing by 8 (the number of 4 byte DWords in 1 unit of URB read).
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
SIMD4x2 mode is only supported by elk which anv doesn't use. iris
doesn't check this. Eventually we should probably just demote the
dispatch_mode field to the stages that still need it.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
