The tex prefetch heuristic simply counts the number of NIR instructions.
Since a vectorized NIR instruction expands to an ir3 instruction per
component, we have to take this into account while counting them.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
After spilling during regular RA, merge sets need to be fixed up. To
find all merge sets, fixup_merge_sets used ra_foreach_dst. However,
after shared RA has run, shared dsts wouldn't have the IR3_REG_SSA flag
set anymore leaving their merge sets lingering. This patch fixes this by
using foreach_dst instead.
Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
The preferred register for merge sets was not updated after allocating
one. This caused a new merge set to be allocated for every register it
contains. This patch fixes this by reusing the update function from the
standard RA.
Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28341>
This accidentally allowed DCC with format conversion, which is not supported.
Also disable EFC with VCN5 for now.
Fixes: 40c3a53fec ("radeonsi: Implement is_video_target_buffer_supported")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30562>
Fixes a "regression" where comically large FPS tests regressed.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 19dba854 ("wsi/x11: Rewrite implementation to always use threads.")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30638>
Currently sequence headers (VPS, SPS, PPS) are always inserted
on each IDR frame and AUD is inserted on every frame, but this
should be decided by application what headers it wants.
AUD is optional and is almost never needed, in some cases sequence
headers also are not needed each IDR frame and currently this only
wastes bits.
With FFmpeg/GStreamer this changes AUD to not be inserted by default,
there is no change to sequence headers as those are already requested
to be inserted on each IDR.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
FFmpeg sends AUD as part of VA_ENC_PACKED_HEADER_SEQUENCE and
VA_ENC_PACKED_HEADER_SLICE.
GStreamer sends it separately as VA_ENC_PACKED_HEADER_RAW_DATA.
It's now also needed to keep track what packed headers were enabled
to include VPS/SPS/PPS with VAEncSequenceParameterBuffer when sequence
packed headers are disabled.
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
Applications should not send types that were not enabled when creating
config and even if they do it will not cause any unexpected issues.
Remove the checks as it is another place that would need to be
updated when adding support for new packed header types.
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30585>
An extra control register word, tpu_tag_cdm_ctrl, will be present when
TPU_DM_GLOBAL_REGISTERS feature is present.
Emit it when it's needed.
The document of this register is available, however I don't think any of
the bits are needed to be set for our current feature set, so just emit
0 now.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30552>
This corresponds to the RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS in the DDK
kernel module source code, and will introduce one more control word to
compute command streams.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30552>
The currently allocated transfer fw_stream buffer lacks the space for a
field that exists conditionally for multicore GPUs, frag_screen.
Enlarge the transfer fw_stream buffer for this field.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30543>
The versioned libgallium library can be confusing on Android, and it is
probably not even needed there, so simplify the build on Android by
always build the unversioned `libgallium_dri.so` overriding the
`-Dunversion-libgallium=true` option added in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30579
Remove also all the bits that deal with the versioned library which are
not needed anymore.
Fixes: 9568976c52 ("android: fix build in multiple ways")
Acked-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30641>
DGC preprocessing is disabled for VBOs, so the dynamic vertex input
should always be initialized. Null VBO descriptors are slightly
different when used with dynamic VS inputs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29831>
