fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 20:08:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4
171993 commits 66 branches 934 tags 1 GiB
Commit graph

171993 commits

This branch
This branch
All branches
Author SHA1 Message Date
Eric Engestrom
ed23e386dc ci/zink+radv: mark flakes as such 
They failed again when I retried, but apparently they are actually
flakes, so mark them as such.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23332>
 2023-05-31 13:19:01 +01:00
Matt Coster
4ba553ab9a pvr: Use common vkGetPhysicalDeviceFeatures2() implementation 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23311>
 2023-05-31 11:55:06 +00:00
Matt Coster
6dab9ea50d pvr: Use correct pbe format for VK_FORMAT_A8B8G8R8_UNORM_PACK32 
Fixes:
  - dEQP-VK.api.image_clearing.core.clear_color_image.1d.linear
      .single_layer.a8b8g8r8_unorm_pack32_71x1
  - dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear
      .single_layer.a8b8g8r8_unorm_pack32_33x128

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: Soroush Kashani <soroush.kashani@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23312>
 2023-05-31 11:38:31 +00:00
Matt Coster
6d3d1f884c pvr: Fix rect splitting logic in pvr_unwind_rects() 
Fixes:
  dEQP-VK.api.copy_and_blit.core.image_to_buffer.buffer_offset_relaxed
  dEQP-VK.api.image_clearing.core.clear_color_image.3d.optimal
    .single_layer.r8_unorm_200x180x16

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: Soroush Kashani <soroush.kashani@imgtec.com>
Reported-by: Oskar Rundgren <oskar.rundgren@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23309>
 2023-05-31 12:23:58 +01:00
Lucas Stach
6611866246 etnaviv: don't flush implicit flush resources when forced 
Resources only need to become visible when the application requested
the context flush, so we can safely skip the flushing when the flush
is forced internally by running out of commandstream space.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23329>
 2023-05-31 09:54:39 +00:00
Lucas Stach
fbd37e6168 etnaviv: update derived state after forced commandstream flush 
If we run out of space in the commandstream while emitting the
current state the drived states won't be recomputed for the
now fully dirty context as the state derivation is called before
any state emitted. Fix this by explicitly updating the derived
state after a forced flush.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8916
CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23329>
 2023-05-31 09:54:39 +00:00
Christian Gmeiner
cb3ac95d03 etnaviv: nir: improve uniform usage for ALU opc 
The current code in lower_alu(..) counts how many const values
are used by one ALU opc. If there are used more then one the
compiler tries to fix this issues by e.g. resolve with a single
combined const src.

We are doing this as some GPUs only allow one const src per
ISA instruction. But it is allowed to use the same const for
multiple srcs.

Lets have a closer look at a real world shader:

impl main {
        /* preds: */
        vec1 32 ssa_0 = load_const (0x3f800000 = 1.000000)
        vec1 32 ssa_1 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_2 = intrinsic load_uniform (ssa_1) (base=0, range=1, dest_type=bool32 /*38*/)       /* u_var */
        vec1 32 ssa_4 = fmul ssa_2.x, ssa_2.y
        vec1 32 ssa_11 = load_const (0x00000000 = 0.000000)
        vec1 32 ssa_13 = seq ssa_2.w, ssa_11
        vec1 32 ssa_6 = fmul ssa_2.z, ssa_13
        vec1 32 ssa_7 = fmul ssa_4, ssa_6
        vec1 32 ssa_9 = deref_var &gl_FragColor (shader_out vec4)
        vec4 32 ssa_10 = vec4 ssa_7, ssa_7, ssa_7, ssa_0
        intrinsic store_deref (ssa_9, ssa_10) (wrmask=xyzw /*15*/, access=0)
        /* succs: block_1 */
        block block_1:
}

The current compiler transforms it to:

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x3f800000 = 1.000000)
        vec4 32 ssa_14 = load_const (0x00000000, 0x00000001, 0x00000002, 0x00000003) = (0.000000, 0.000000, 0.000000, 0.000000)
        vec2 32 ssa_15 = load_const (0x00000000, 0x00000001) = (0.000000, 0.000000)
        vec1 32 ssa_4 = fmul ssa_15.x, ssa_15.y
        vec2 32 ssa_16 = load_const (0x00000003, 0x00000000) = (0.000000, 0.000000)
        vec1 32 ssa_13 = seq ssa_16.x, ssa_16.y
        vec1 32 ssa_6 = fmul ssa_14.z, ssa_13
        vec1 32 ssa_7 = fmul ssa_4, ssa_6
        vec1 32 ssa_9 = deref_var &gl_FragColor (shader_out vec4)
        vec1 32 ssa_17 = mov ssa_0
        vec4 32 ssa_10 = vec4 ssa_7, ssa_7, ssa_7, ssa_17
        intrinsic store_deref (ssa_9, ssa_10) (wrmask=xyzw /*15*/, access=0)
        /* succs: block_1 */
        block block_1:
}

There is no need to create ssa_15 as we can use ssa_14 for the first fmul.

With this change the compiler creates the following shader:

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x3f800000 = 1.000000)
        vec4 32 ssa_14 = load_const (0x00000000, 0x00000001, 0x00000002, 0x00000003) = (0.000000, 0.000000, 0.000000, 0.000000)
        vec1 32 ssa_4 = fmul ssa_14.x, ssa_14.y
        vec2 32 ssa_15 = load_const (0x00000003, 0x00000000) = (0.000000, 0.000000)
        vec1 32 ssa_13 = seq ssa_15.x, ssa_15.y
        vec1 32 ssa_6 = fmul ssa_14.z, ssa_13
        vec1 32 ssa_7 = fmul ssa_4, ssa_6
        vec1 32 ssa_9 = deref_var &gl_FragColor (shader_out vec4)
        vec1 32 ssa_16 = mov ssa_0
        vec4 32 ssa_10 = vec4 ssa_7, ssa_7, ssa_7, ssa_16
        intrinsic store_deref (ssa_9, ssa_10) (wrmask=xyzw /*15*/, access=0)
        /* succs: block_1 */
        block block_1:
}

This change reduces immediate pressure and reduces spend CPU cycles.

No piglit or deqp regression seen.

shader-db results for GC2000:

total instructions in shared programs: 955128 -> 955128 (0.00%)
instructions in affected programs: 0 -> 0
helped: 0
HURT: 0

total temps in shared programs: 85689 -> 85689 (0.00%)
temps in affected programs: 0 -> 0
helped: 0
HURT: 0

total immediates in shared programs: 155428 -> 155240 (-0.12%)
immediates in affected programs: 1840 -> 1652 (-10.22%)
helped: 34
HURT: 1
helped stats (abs) min: 4 max: 16 x̄: 5.65 x̃: 4
helped stats (rel) min: 2.94% max: 33.33% x̄: 16.92% x̃: 16.67%
HURT stats (abs)   min: 4 max: 4 x̄: 4.00 x̃: 4
HURT stats (rel)   min: 14.29% max: 14.29% x̄: 14.29% x̃: 14.29%
95% mean confidence interval for immediates value: -6.57 -4.17
95% mean confidence interval for immediates %-change: -19.83% -12.23%
Immediates are helped.

total loops in shared programs: 0 -> 0
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   0
GAINED: 0

Total CPU time (seconds): 102.55 -> 96.35 (-6.05%)

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23323>
 2023-05-31 09:19:29 +00:00
Hans-Kristian Arntzen
5266bb0211 Fix DGC bug where indirect count > maxSequencesCount. 
Need to explicitly clamp the indirect count against maxSequencesCount,
or we risk writing bogus commands into spill region.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23252>
 2023-05-31 07:49:54 +00:00
Samuel Pitoiset
1947500208 aco: remove nir_intrinsic_load_barycentric_at_sample occurences 
This is lowered earlier and shouldn't get there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23307>
 2023-05-31 07:25:46 +00:00
Dave Airlie
54ceec8d9e radv/meta: fix uninitialised stack memory usage. 
==10199== Conditional jump or move depends on uninitialised value(s)
==10199==    at 0xA107B13: radv_resume_queries (radv_meta.c:93)
==10199==    by 0xA108097: radv_meta_restore (radv_meta.c:225)
==10199==  Uninitialised value was created by a stack allocation
==10199==    at 0xA1145B2: fill_buffer_shader (radv_meta_buffer.c:171)

saved_state is never memset, so the value should be inited.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23327>
 2023-05-31 06:52:46 +00:00
Vinson Lee
ed2d771931 r600/sfn: Initialize BlockScheduler member m_chip_family. 
Fix defect reported by Coverity Scan.

Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member m_chip_family is not initialized
in this constructor nor in any functions that it calls.

Fixes: e57643cf54 ("r600/sfn: Add handling for R600 indirect access alias handling")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23290>
 2023-05-31 06:18:47 +00:00
Lucas Fryzek
673acc3d01 v3dv: Update texture padding logic to match v3d changes 
Piglit tests for v3d highlighted issues with the padding
computation when allocating memory for slices. This change
moves the fixes from v3d to v3dv.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23260>
 2023-05-31 05:27:08 +00:00
Lucas Fryzek
10b4b3bf3f v3d: Add support for ASTC texture compression 
Add proper support for ASTC texture compression in the v3d
gallium driver, instead of relying on the fallback software
conversion from gallium, as the hardware has native support
for ASTC compressed textures.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23260>
 2023-05-31 05:27:08 +00:00
Mike Blumenkrantz
0a3ddcbe8b vulkan: use cmd size array for queued cmd allocations 
minor simplification for consistency

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23322>
 2023-05-31 03:13:22 +00:00
Mike Blumenkrantz
fd45ab843f vulkan/cmd_queue: expose cmd sizes 
now that cmds are more precisely allocated, it's necessary for drivers
to have some way to determine what the allocation size is

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23322>
 2023-05-31 03:13:22 +00:00
Mike Blumenkrantz
5759ab668e vulkan/cmd_queue: allocate cmds based on the size of the cmd 
the base size of a vk_cmd_queue_entry is massive since there are a couple
union entries that have a trillion params. by allocating conditionally using
the union member size, memory can be reduced, which will affect some user-facing
api properties

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23322>
 2023-05-31 03:13:22 +00:00
Mike Blumenkrantz
96a404cf82 vulkan: reorder vk_cmd_queue_entry 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23322>
 2023-05-31 03:13:22 +00:00
Julia Tatz
223c0ecd1e zink/ci: update expected results 
Remove the now passing arb_compute_variable_group_size tests

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23244>
 2023-05-31 02:48:33 +00:00
Julia Tatz
2f3841339c zink: fix layout(local_size_variable) for vk1.3+ 
Use the correct exec-mode op for LocalSizeId
Corrected typo `gl_LocalGroupSize` -> `gl_LocalGroupSizeARB`

Fixes: 99bd1eaf ("zink: use spir-v 1.6 local-size when needed")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23244>
 2023-05-31 02:48:33 +00:00
Yiwei Zhang
112e16b14d docs/venus: advertise VK_EXT_image_2d_view_of_3d 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23090>
 2023-05-30 22:52:12 +00:00
Yiwei Zhang
2db9536ade venus: enable VK_EXT_image_2d_view_of_3d 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23090>
 2023-05-30 22:52:12 +00:00
Yiwei Zhang
83018a7854 venus: sync protocol for VK_EXT_image_2d_view_of_3d 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23090>
 2023-05-30 22:52:11 +00:00
Yiwei Zhang
c18b7a2082 venus: sync to latest protocol from header v1.3.248 
This is to make later protocol update CL to be easily backported to
older branches.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23090>
 2023-05-30 22:52:11 +00:00
Yiwei Zhang
2b551d100b venus: silence -Wuninitialized 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23090>
 2023-05-30 22:52:11 +00:00
Mark Janes
d0669f3ede intel/dev: switch defect identifiers to use lineage numbers 
Update existing workarounds when necessary to match changed
identifiers.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23226>
 2023-05-30 22:13:41 +00:00
Rob Clark
b94d35f74d freedreno: Reallocate on unshared export 
If we need to export a handle on a resource which was not originally
allocated with PIPE_BIND_SHARED, then re-allocate with shared flag and
try again.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9110
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23324>
 2023-05-30 21:37:13 +00:00
Rob Clark
75193262fd freedreno: Add aux-context support 
A global aux-context can be created on-demand for cases where we need to
(for example) blit a resource when we only have a screen ptr.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23324>
 2023-05-30 21:37:12 +00:00
Rob Clark
221a6986ba freedreno: Handle export error handling 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23324>
 2023-05-30 21:37:12 +00:00
Rob Clark
7cc8185ca3 freedreno/drm: Don't try to export suballoc bo 
Suballoc BOs don't have a real handle, so attempting to dmabuf export
won't work.  Likewise for handle or flink-name export.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23324>
 2023-05-30 21:37:12 +00:00
Alyssa Rosenzweig
be705ce760 nir/print: Print locations for geometry shader inputs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23259>
 2023-05-30 16:25:07 -04:00
Alyssa Rosenzweig
065db2ddad intel/blorp: Use nir_trim_vector 
With Coccinelle patch:

@@
expression b, V;
@@

-nir_vec2(b, nir_channel(b, V, 0), nir_channel(b, V, 1))
+nir_trim_vector(b, V, 2)

@@
expression b, V;
@@

-nir_vec3(b, nir_channel(b, V, 0), nir_channel(b, V, 1), nir_channel(b, V, 2))
+nir_trim_vector(b, V, 3)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23259>
 2023-05-30 16:24:21 -04:00
Alyssa Rosenzweig
4486009edb radv/query: Use nir_trim_vector 
With Coccinelle patch:

@@
expression b, V;
@@

-nir_vec2(b, nir_channel(b, V, 0), nir_channel(b, V, 1))
+nir_trim_vector(b, V, 2)

@@
expression b, V;
@@

-nir_vec3(b, nir_channel(b, V, 0), nir_channel(b, V, 1), nir_channel(b, V, 2))
+nir_trim_vector(b, V, 3)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23259>
 2023-05-30 16:24:21 -04:00
Alyssa Rosenzweig
2b2685f551 pan/lower_framebuffer: Use nir_replicate 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23259>
 2023-05-30 16:24:21 -04:00
Alyssa Rosenzweig
ebf4eff7eb treewide: Use nir_replicate 
Via coccinelle.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23259>
 2023-05-30 16:24:21 -04:00
Alyssa Rosenzweig
f534c2c539 nir/builder: Add nir_replicate helper 
Splat a scalar to all components of a vector.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23259>
 2023-05-30 16:24:21 -04:00
Veerabadhran Gopalakrishnan
11c8b84c53 radeonsi: return kernel queried video capability for HEVC and JPEG 
Query and return the values obtained from kernel for VCN_1 and above.
Earlier the HEVC and JPEG capabilities were returned based on
pre-defined values.

Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23067>
 2023-05-30 19:15:12 +00:00
Veerabadhran Gopalakrishnan
af8f04e9fe radeonsi: return kernel queried video capability for HEVC and JPEG 
Query and return the values obtained from kernel for VCN_1 and above.
Earlier the HEVC and JPEG capabilities were returned based on
pre-defined values.

Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23067>
 2023-05-30 19:15:12 +00:00
Konstantin Seurer
a2ae6518c2 gallivm: Fix gather/scatter types for newer llvm 
The types changed with opaque pointer support.

Fixes a bunch of lavapipe regressions.
Cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23293>
 2023-05-30 18:25:49 +00:00
Eric Engestrom
74704cbb18 docs/calendar: add 23.2 branchpoint and release candidates 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23205>
 2023-05-30 18:20:20 +00:00
Dylan Baker
631109f8f7 docs: update calendar for 23.0.4 
At this point I'm calling 23.0 done. Please use 23.1 for future updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23325>
 2023-05-30 18:15:28 +00:00
Dylan Baker
cf2a9e2c15 docs: Add sha256 sum for 23.0.4 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23325>
 2023-05-30 18:15:28 +00:00
Dylan Baker
d4f612b30d docs: add release notes for 23.0.4 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23325>
 2023-05-30 18:15:28 +00:00
Jesse Natalie
84691dfc46 microsoft/compiler: Use image formats to determine texture types 
Fixes some tests when bindless is disabled, where the image format is
R32, we do atomics on it, but we didn't set the "typed UAV load with
additional formats" feature bit because when we loaded from it, we
only loaded one component. Since the image format on the DXIL side
was declared as U32x4, the DXIL validator said that we should have.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23266>
 2023-05-30 17:54:18 +00:00
Jesse Natalie
431557e38e spirv2dxil: Assign formats to image vars before lowering to bindless 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23266>
 2023-05-30 17:54:18 +00:00
Jesse Natalie
a66d1e4d1f microsoft/compiler: Add a pass to assign image formats based on number of components 
For loads/stores without formats, let's guess one based on how it's used.
The actual format doesn't matter, we just want to use it for the number
of components it has.

Also copy image formats from variables to intrinsics, to ensure that
deref-based intrinsics have formats assigned and lowered intrinsics
are up to date.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23266>
 2023-05-30 17:54:18 +00:00
Jesse Natalie
0c8c77b1b0 microsoft/compiler: Enable emitting type info for textures with <4 comps 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23266>
 2023-05-30 17:54:18 +00:00
Hans-Kristian Arntzen
a3507f9d87 radv/amdgpu: Report 48-bit VAs in bo logs. 
More ergonomic when correlating with page fault addresses.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23256>
 2023-05-30 17:17:58 +00:00
Chia-I Wu
063e2e8ed8 radv: fix gl_SampleMaskIn for sample shading 
When sample shading, we need

  gl_SampleMaskIn = SampleCoverage & (PsIterMask << gl_SampleID);

Add a new shader arg, ps_iter_mask, to pass PsIterMask to ps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23265>
 2023-05-30 16:35:31 +00:00
Chia-I Wu
0bba0eb0df ac, radeonsi: add and use ac_get_ps_iter_mask 
It is more natural for ac_get_ps_iter_mask to take sample count.
Replace samplemask_log_ps_iter by ps_iter_smples in
ac_nir_lower_ps_options accordingly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23265>
 2023-05-30 16:35:30 +00:00
Chia-I Wu
750d641ca6 aco: fix alignment check in emit_load 
align_offset already takes const_offset into consideration.  Remove the
adjustment.

Fixes: 542733dbbf ("aco: add emit_load helper")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9097
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23242>
 2023-05-30 16:02:34 +00:00