Commit graph

79279 commits

Author SHA1 Message Date
Jason Ekstrand
ecfb074276 anv/allocator: Make the bo_pool dynamically sized 2016-03-18 17:25:58 -07:00
Jason Ekstrand
b1c5d45872 anv/allocator: Add a size field to bo_pool_alloc 2016-03-18 11:50:53 -07:00
Jordan Justen
3fd308a357 Merge remote-tracking branch 'origin/master' into vulkan 2016-03-17 01:44:07 -07:00
Jordan Justen
7d021cb15e i965/nir: Lower nir compute shader shared variables
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-17 01:23:40 -07:00
Jordan Justen
b1e7cdfdcf nir: Lower shared var atomics during nir_lower_io
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-17 01:23:40 -07:00
Jordan Justen
e3cbb9d37c nir: Add support for lowering load/stores of shared variables
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-17 01:23:40 -07:00
Jordan Justen
683c359c54 nir: Add atomic operations on variables
This allows us to first generate atomic operations for shared
variables using these opcodes, and then later we can lower those to
the shared atomics intrinsics with nir_lower_io.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-17 01:23:40 -07:00
Jordan Justen
3c807607df nir: Add compute shader shared variable storage class
Previously we were receiving shared variable accesses via a lowered
intrinsic function from glsl. This change allows us to send in
variables instead. For example, when converting from SPIR-V.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-17 01:23:40 -07:00
Jordan Justen
26f8262698 nir/print: Add space after shader_storage var mode
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-03-17 01:23:40 -07:00
Iago Toral Quiroga
5be11d2236 i965: Skip execution size adjustment for instructions of width 4
This code in brw_set_dest adjusts the execution size of any instruction
with a dst.width < 8. However, we don't want to do this with instructions
operating on doubles, since these will have a width of 4, but still
need an execution size of 8 (for SIMD8). Unfortunately, we can't just check
the size of the operands involved to detect if we are doing an operation on
doubles, because we can have instructions that do operations on double
operands interpreted as UD, operating on any of its 2 32-bit components.

Previous commits have made it so we never emit instructions with a horizontal
width of 4 that don't have the correct execution size set for gen6+, so
we can skip it in this case, avoiding the conflicts with fp64 requirements.

Expanding the same fix to other hardware generations requires many more
changes but since we are not targetting fp64 support on them
wer don't really care for now.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:25 +01:00
Samuel Iglesias Gonsalvez
22a10dd030 i965/vec4/gen6: fix exec_size for MOV with a width of 4 in generate_gs_ff_sync()
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:25 +01:00
Samuel Iglesias Gonsalvez
b91b9e4b00 i965/vec4/gen6: fix exec_size for instructions with destination width of 4
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:25 +01:00
Samuel Iglesias Gonsalvez
30fc3fa24d i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs_svb_write()
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:25 +01:00
Samuel Iglesias Gonsalvez
2fafc6b98c i965/gs/gen6: fix execsize for instructions with width of 4 in gen6_sol_program()
v2:
- Add assert (Topi).

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:25 +01:00
Iago Toral Quiroga
f6342b5645 i965: set correct execsize for MOVS with a width of 4 in brw_find_live_channel
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:25 +01:00
Iago Toral Quiroga
31a8604252 i965/eu: set execution size for SEND message in brw_send_indirect_message
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:25 +01:00
Iago Toral Quiroga
2d6af62a0f i965/fs: Set exec size for gen7 pull const loads
v2 (Topi):
  - No need to set the execsize for the indirect send message,
    the next patch will handle that.
  - Set the execution size explicitly instead of taking it from
    the width of the dst that we set before.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:24 +01:00
Iago Toral Quiroga
ea45b6e96d i965/eu: set correct execution size in brw_NOP
v2: NOP should have an execsize of 1 (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-17 08:23:24 +01:00
Kenneth Graunke
9c1e01c4a8 meta: Don't use integer handles for shaders or programs.
Previously, we gave our internal clear/blit shaders actual GL handles
and stored them in the shader/program hash table.  We used ordinary
GL API entrypoints to work with them.

We thought this shouldn't be a problem because GL doesn't allow
applications to invent their own names for shaders or programs.
GL allocates all names via glCreateShader and glCreateProgram.

However, having them in the hash table is a bit risky: if a broken
application guesses the name of our shaders or programs, it could
alter them, potentially screwing up future meta operations.

Also, test cases can observe the programs in the hash table.  Running
a single dEQP process that executes the following test list:

dEQP-GLES3.functional.negative_api.buffer.clear
dEQP-GLES3.functional.negative_api.shader.compile_shader
dEQP-GLES3.functional.negative_api.shader.delete_shader

would result in the last two tests breaking.  The compile_shader test
calls glCompileShader(9) straight away, and since it hasn't even created
any shaders or programs, it expects to get a GL_INVALID_VALUE error
because there's no such name.  However, because the clear test ran
first, it created Meta programs, so an object named "9" did exist.

This patch reworks Meta to work with gl_shader and gl_shader_program
pointers directly.  These internal programs have bogus names, and are
never stored in the hash tables, so they're invisible to applications.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94485
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-16 23:57:11 -07:00
Kenneth Graunke
0fe254168b mesa: Expose compile_shader() and link_program() beyond the file.
This will allow me to use them directly from Meta, bypassing the
versions that work with GL integer handles.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-03-16 23:57:11 -07:00
Kenneth Graunke
7753657cf2 mesa: Make link_program() take a gl_shader_program, not a GLuint.
In half the callers, we already have a pointer, and don't need
to look it up again.  This will also help with upcoming meta work.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-03-16 23:57:11 -07:00
Kenneth Graunke
a461e0003f mesa: Make compile_shader() take a gl_shader, not a GLuint.
In half the callers, we already have a pointer, and don't need
to look it up again.  This will also help with upcoming meta work.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-03-16 23:57:11 -07:00
Kenneth Graunke
a7e9b31d5b meta: Use the _mesa_meta_compile_and_link_program helper more places.
Less boilerplate.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-03-16 23:57:11 -07:00
Eric Anholt
2b9f0dffe0 vc4: Move discard handling to the condition flag.
Now that the field exists in the instruction, we can make discards less
special.  As a bonus, that means that we should be able to merge some more
.sf instructions together when we get around to that.

This causes some scheduling changes, as it allows tlb_color_reads to be
delayed past the discard condition setup.  Since the tlb_color_read ends
up later, this may mean performance improvements, but I haven't tested.

total instructions in shared programs: 78114 -> 78035 (-0.10%)
instructions in affected programs:     1922 -> 1843 (-4.11%)
total estimated cycles in shared programs: 234318 -> 234329 (0.00%)
estimated cycles in affected programs:     8200 -> 8211 (0.13%)
2016-03-16 11:28:47 -07:00
Eric Anholt
7c9fc43915 vc4: Don't make a temporary for setting flags.
The register allocator doesn't really do anything about the temp, so it
doesn't seem like it should matter.  However, the scheduler would think
that a new def is being created.

This doesn't change anything yet, but it avoids a bunch of regressions in
the next commit.
2016-03-16 11:28:34 -07:00
Eric Anholt
b4f45f319c vc4: Add a safety check for setting flags.
If a pack was on the src reg, should it be a float, int, or mul unpack?
Just complain, instead.
2016-03-16 11:28:34 -07:00
Eric Anholt
a298fb15af vc4: Reuse list_for_each_entry_safe_rev().
This didn't exist when I wrote the code.
2016-03-16 11:28:34 -07:00
Nanley Chery
5464f0c046 anv/blit: Reduce number of VUE headers being read
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:57:23 -07:00
Nanley Chery
f33866ae0a anv/blit: Remove completed finishme for VkFilter
This task was finished as of:
d9079648d0.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:57:19 -07:00
Nanley Chery
5647de8ba5 anv/blit2d: Only use one extent in meta_emit_blit2d
Since scaling isn't involved, we don't need multiple extents.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:57:14 -07:00
Nanley Chery
92fb65f117 anv/blit2d: Remove sampler from pipeline
Since we're using texelFetch with a sampled image, a sampler is no
longer needed. This agrees with the Vulkan Spec section 13.2.4
Descriptor Set Updates:

sampler is a sampler handle, and is used in descriptor updates for types
VK_DESCRIPTOR_TYPE_SAMPLER and VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
if the binding being updated does not use immutable samplers.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:57:00 -07:00
Nanley Chery
f8f9886915 anv/blit2d: Use texel fetch in frag shader
The texelFetch operation requires that the sampled texture coordinates
be unnormalized integers. This will simplify the copy shader for
w-tiled images (stencil buffers).

v2 (Jason):
   Use f2i for texel coords
   Fix num_components indirectly
   Use float inputs for interpolation
   Nest tex_pos functions

Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:56:51 -07:00
Nanley Chery
b487acc489 Revert "anv/meta: Make meta_emit_blit() public"
This reverts commit f391683922.

Some conflicts had to be resolved in order for this revert to be
successful.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:56:46 -07:00
Nanley Chery
1a0c63b880 Revert "anv/meta: Prefix anv_ to meta_emit_blit()"
This reverts commit 514c055717.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:56:41 -07:00
Nanley Chery
997a873f0c anv/blit2d: Customize meta blit structs and functions for blit2d API
* Add fields in meta struct
* Add support in meta init/teardown
* Switch to custom meta_emit_blit2d()

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:56:22 -07:00
Nanley Chery
2d8c632117 anv/blit2d: Copy anv_meta_blit.c functions
These will be customized for blit2d operations.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-03-16 10:56:10 -07:00
Kenneth Graunke
b566317e7e meta: Use ARB_explicit_attrib_location in the rest of the meta shaders.
This is cleaner than using glBindAttribLocation().

Not all drivers support the extension, but I don't think those drivers
use GLSL in the first place.  Apparently some Meta shaders already use
GL_ARB_explicit_attrib_location, so I think it should be okay.

Honestly, I'm not sure how the old code worked anyway - we bound the
attribute location for "texcoords", while all the shaders capitalized
or spelled it differently.

v2: Convert another instance in brw_meta_fast_clear.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-03-16 00:09:56 -07:00
Plamena Manolova
9d9965c06f mesa: Ignore glPointSize when GL_POINT_SIZE_ARRAY_OES is enabled
When a user defines a point size array and enables it, the point
size value set via glPointSize should be ignored. To achieve this,
we can simply toggle ctx->VertexProgram.PointSizeEnabled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42187
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-03-15 15:49:48 -07:00
Jason Ekstrand
abaa3bed22 anv/device: Flush the fence batch rather than the start of the BO 2016-03-15 15:24:24 -07:00
Jason Ekstrand
7f6a0cb29c Merge remote-tracking branch 'public/master' into vulkan 2016-03-15 14:09:50 -07:00
Varad Gautam
e103b52aec vc4: Coalesce instructions using VPM reads into the VPM read.
This is done instead of copy propagating the VPM reads into the
instructions using them, because VPM reads have to stay in order.

shader-db results:
total instructions in shared programs: 78509 -> 78114 (-0.50%)
instructions in affected programs:     5203 -> 4808 (-7.59%)
total estimated cycles in shared programs: 234670 -> 234318 (-0.15%)
estimated cycles in affected programs:     5345 -> 4993 (-6.59%)

Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Rhys Kidd <rhyskidd@gmail.com>
2016-03-15 13:09:24 -07:00
Varad Gautam
00bdbb22a9 vc4: rename file to group vpm optimizations together
This file will contain optimization passes for both vpm reads
and writes.

Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-03-15 12:49:37 -07:00
Eric Anholt
1c4b077409 vc4: Fix failures with nir_extract_* since the addition of the opcodes. 2016-03-15 12:49:37 -07:00
Roland Scheidegger
bb2c5e657b llvmpipe: fix lp_rast_plane alignment on 32bit
Some rasterization code relies (for sse) on the first and third planes
(but not the second for now) being 128bit aligned, and we didn't get that
on 32bit - I mistakenly thought the 64bit number in the struct would get
the thing aligned to 64bit even on 32bit archs.
Stephane Marchesin really figured this out.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

CC: <mesa-stable@lists.freedesktop.org>
2016-03-15 19:42:15 +01:00
Roland Scheidegger
12a4f0bed6 draw: fix line stippling
The logic was comparing actual ints, not true/false values.
This meant that it was emitting always multiple line segments instead of just
one even if the stipple test had the same result, which looks inefficient, and
the segments also overlapped thus breaking line aa as well.
(In practice, with the no-op default line stipple pattern, for a 10-pixel
long line from 0-9 it was emitting 10 segments, with the individual segments
ranging from 0-1, 0-2, 0-3 and so on.)

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94193

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

CC: <mesa-stable@lists.freedesktop.org>
2016-03-15 19:41:34 +01:00
Roland Scheidegger
4b249ed4cd softpipe: fix misleading TGSI_QUAD_SIZE usage
All these img filter loops iterate through NUM_CHANNELS, not QUAD_SIZE.
In practice both are of course the same unchangeable value (4), but it
makes the code look a bit confusing. Moreover, some of the functions were
actually given an array of 4 values according to the declaration, yet the
code was addressing values 0/4/8/12 out of it, so fix this by just saying
it's a pointer to floats like the other functions.

While here, also add comment about not quite correct filtering.

There's no actual code difference.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-15 19:37:59 +01:00
Roland Scheidegger
9e9d69979c softpipe: fix anisotropic filtering crash
The filt_args->offset wasn't assigned but was always used later leading
to a crash (as far as I can tell, texel offsets don't actually make much
sense with anisotropic filtering, but because there's no explicit setting
if offsets are enabled there the array is always accessed).

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94481

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>

CC: <mesa-stable@lists.freedesktop.org>
2016-03-15 16:40:05 +01:00
Nicolai Hähnle
4de25fa7b0 radeonsi: set DEPTH_BEFORE_SHADER based on FS_EARLY_DEPTH_STENCIL
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-14 17:24:59 -05:00
Nicolai Hähnle
0ffcc318e6 tgsi: add tgsi_full_src_register_from_dst helper function
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-14 17:24:49 -05:00
Nicolai Hähnle
c02d73af0b gallium/u_inlines: add util_copy_image_view
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-14 17:24:46 -05:00