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i965/gs/gen6: fix execsize for instructions with width of 4 in gen6_sol_program()

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v2:
- Add assert (Topi).

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Samuel Iglesias Gonsalvez 2015-12-03 18:05:39 +01:00 • committed by Samuel Iglesias Gonsálvez
parent f6342b5645
commit 2fafc6b98c
1 changed files with 10 additions and 1 deletions
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11
src/mesa/drivers/dri/i965/brw_ff_gs_emit.c
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@ -406,9 +406,13 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
: 0x00020001)); /* (1, 0, 2) */
brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL);
}
assert(c->reg.destination_indices.width == BRW_EXECUTE_4);
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_4);
brw_ADD(p, c->reg.destination_indices,
c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
brw_pop_insn_state(p);
/* For each vertex, generate code to output each varying using the
* appropriate binding table entry.
*/
@ -438,8 +442,13 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
vertex_slot.swizzle = varying == VARYING_SLOT_PSIZ
? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_4);
brw_MOV(p, stride(c->reg.header, 4, 4, 1),
retype(vertex_slot, BRW_REGISTER_TYPE_UD));
brw_pop_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_svb_write(p,
final_write ? c->reg.temp : brw_null_reg(), /* dest */