Commit graph

88115 commits

Author SHA1 Message Date
Samuel Pitoiset
ecf04b84e5 radeonsi: replace ctx->soa.outputs by ctx->outputs
The plan is to replace si_shader_context::soa with its parent
structure (ie. bld_base).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 10:41:06 +01:00
Samuel Pitoiset
f04088a7ba radeonsi: move si_shader_context::soa::addr to si_shader_context
The plan is to replace si_shader_context::soa with its parent
structure (ie. bld_base).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 10:41:02 +01:00
Samuel Pitoiset
6f0d955b6d radeonsi: allocate the array of immediates dynamically
Currently, we can store up to 256 immediates in a static array,
but this is not always enough. Instead, allocate a dynamic array
like what we currently do for temps.

This fixes a segfault with
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23

No regressions found with full piglit run.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 10:40:57 +01:00
Grazvydas Ignotas
cb89d19dbb radv: remove some unused macros and functions
These seem unlikely to be used.
Also remove irrelevant comment about SKL.

v2: forgot to rebase on master

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
2017-01-13 08:42:33 +01:00
Nanley Chery
64272d4f1b anv: Avoid some resolves for samplable HiZ buffers
v2: Simplify nested ifs (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:21 -08:00
Nanley Chery
71334f494a anv: Enable sampling from HiZ
v2: Restrict ISL_AUX_USAGE_HIZ to depth aspects

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:21 -08:00
Nanley Chery
5e0902cd2a anv/blorp: Don't fast depth clear samplable HiZ buffers on BDW
Avoid the resolves that would be required if fast depth clears were
allowed for such buffers.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:21 -08:00
Nanley Chery
3ac01ad2ac anv: Add a helper to determine sampling with HiZ
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
bcf880a9c8 isl/surface_state: Handle ISL_AUX_USAGE_HIZ
v2: Remove redundant x/y offset asserts (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
58af615636 anv: Perform HiZ resolves only on layout transitions
This is a better mapping to the Vulkan API and improves performance in
all tested workloads.

v2: Remove unnecessary image view aspect checks (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
2852efcda4 anv: Disable HiZ for input attachments
v2 (Jason Ekstrand):
- Add spec citation
- Drop conditional

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
b62d8ad2ae anv: Avoid resolves incurred by fast depth clears
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
968ffd6c86 anv: Prepare for transitioning to the requested final layout
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
104ce1dbab anv: Store depth stencil layouts
Store the current and requested depth stencil layouts so that we can
perform the appropriate HiZ resolves for a given transition while
recording a render pass.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
2e2cf78a51 anv: Add helpers to handle depth buffer layout transitions
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
0ce8b37a8e anv: Delete anv's HiZ op emit function
This is no longer used.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
462a4c9648 anv: Use the gen8 BLORP HiZ resolving function
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
d16871d958 anv/blorp: Add a gen8 HiZ op resolve function
Add an entry point for resolving using BLORP's gen8 HiZ op function.

v2: Manually add the aux info

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
3b7106c181 anv: Use gen8 BLORP HiZ clearing functions
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:20 -08:00
Nanley Chery
f357af0c90 intel/blorp_clear: Add gen8 HiZ clearing functions
Add an entry point for the optimized gen8 BLORP HiZ sequence. commit
c9eaf12de2 fixed a bug that was
unknowingly worked around by forcing additional clear rectangle
alignment restrictions not specified in the PRMs. Now that the bug is no
longer present, omit the additional alignment restrictions.

v2: Adjust code comment about padding

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:19 -08:00
Nanley Chery
64fb5b0d51 anv: Enable HiZ support for multiple subpasses
We'll be using layout transitions later on in the series which can occur
within and between subpasses. Turn this on now to simplify the change
later.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:19 -08:00
Nanley Chery
168985fca1 anv: Use ::anv_attachment_state for toggling HiZ per subpass
We're about to enable HiZ support for multiple subpasses. Use this field
to keep track of whether or not subpass operations should treat the
depth buffer as having an auxiliary HiZ buffer.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:19 -08:00
Nanley Chery
055ff2ec52 anv: Replace anv_image_has_hiz() with ISL_AUX_USAGE_HIZ
The helper doesn't provide additional functionality over the current
infrastructure.

v2: Add comment to anv_image::aux_usage (Jason Ekstrand)
v3: Clarify comment for aux_usage (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:19 -08:00
Nanley Chery
160a54810e anv/blorp: Handle ISL_AUX_USAGE_HIZ
Prevent assert failures that would occur in the next patch.

v2: Don't remove asserts from blorp/blit (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:19 -08:00
Nanley Chery
09948151ab intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP
We'll be switching to layout-transition based resolves which can occur
outside of a render pass. Add this sequence to BLORP, as using BLORP
will enable emitting depth stencil state outside of a render pass (among
other benefits). The depth buffer extent is ignored to enable eventual
usage in VkCmdClearAttachments().

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 20:52:19 -08:00
Emil Velikov
f0bdd13fdb get-typod-pick-list.sh: add new script
Typos do happen as people nominate patches for stable. This script aims
to catch most of those.

Due to the subtle nature of things, one has to pay special attention to
the output, similar to get-extra-pick-list.sh.

At the moment only the following is handled:
 grep -i "CC:.*mesa-dev"

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-13 03:07:48 +00:00
Emil Velikov
5abd0a7583 ac: automake: ensure that ./common is generated
Depending on the autoconf (or friends) version one may or may not have
the ./common folder created. Thus in the latter case we'll fail to
generate the file.

Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Darren Salt <devspam@moreofthesa.me.uk>
Reported-by: Darren Salt <devspam@moreofthesa.me.uk>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-13 03:07:48 +00:00
Ilia Mirkin
f897036978 nvc0/ir: only try to check for zero LOD if we aren't already forcing it
There's a levelZero flag which forces texturing to pick level zero (and
not consume an explicit LOD argument). This is set for MS targets, but
could also be set for any other incoming instruction. As that is what
determines whether a LOD argument is present, check that rather than the
more indirect isMS logic.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-01-12 21:08:42 -05:00
Ilia Mirkin
eb60a89bc3 nouveau: take extra push space into account for pushbuf_space calls
Ever since a long time ago when I messed around with fences, I ensure
that after a PUSH_SPACE call there is enough space to write a fence out
into the pushbuf.

However the PUSH_SPACE macro is not all-knowing, and so sometimes we
have to invoke nouveau_pushbuf_space manually with the relocs/pushes
args set. If we don't take the extra allocation from PUSH_SPACE into
account, then we will end up accidentally flushing when the code was not
expecting a flush. This can lead to various runtime and rendering
failures.

The amount of extra allocation isn't that important - it has to be at
least 8 based on the current nouveau_winsys.h setting, but even more
won't hurt. I just rounded up to powers of 2.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99354
Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Ben Skeggs <bskeggs@redhat.com>
2017-01-12 20:39:19 -05:00
Grazvydas Ignotas
8945836658 mapi: update the asm code to support x32
Fixes crashes when both glx-tls and asm are enabled on x32.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94512
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=575458
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2017-01-13 00:59:32 +01:00
Nicolai Hähnle
1007047ca1 ac/nir: use ac_emit_fdiv throughout
... and eliminate emit_fdiv and nir_to_llvm_context::fpmath_md_*, which
are now unused.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:39:22 +01:00
Nicolai Hähnle
38c67f77ed ac/nir: use ac_build_gather_values[_extended] throughout
... and eliminate the non-ac copies. Mostly straight-forward
search & replace.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:39:20 +01:00
Nicolai Hähnle
2c9d26a356 ac/nir: use ac_emit_llvm_intrinsic throughout
... by straight-forward search & replace, and eliminate
emit_llvm_intrinsic.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:39:17 +01:00
Nicolai Hähnle
fccf29373d radeonsi: remove unused si_prepare_cube_coords
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:39:13 +01:00
Nicolai Hähnle
a0ce09b4b2 amd/common: unify cube map coordinate handling between radeonsi and radv
Code is taken from a combination of radv (for the more basic functions,
to avoid gallivm dependencies) and radeonsi (for the new and improved
derivative calculations).

v2: add 0.5 offset to tex coords only after derivative calculation

v3:
- really only touch the first three coordinates
- rebase on the removal of the 1.5 --> 0.5 offset change

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:39:10 +01:00
Nicolai Hähnle
0ee1ee5fbb radeonsi: only touch first three coordinates in si_prepare_cube_coords
Sourcing coords_arg[4] is actually never correct, since bias is handled
differently in tex_fetch_args anyway.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:39:07 +01:00
Nicolai Hähnle
9f590ee9d9 radeonsi: remove unused si_llvm_cube_to_2d_coords
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:39:03 +01:00
Nicolai Hähnle
205ad5234a radeonsi: restrict cube map derivative computations to the correct plane
As remarked by the comment in the original code, the old algorithm fails when
(tc + deriv) points at a different cube face. Instead, simply project the
derivative directly to the plane of the selected cube face.

The new code is based on exactly differentiating (using the chain rule)
the projection onto a plane corresponding to a fixed cube map face (which
is still selected in the usual way based on the texture coordinate itself).
The computations end up fairly involved, but we do save two reciprocal
computations.

Fixes GL45-CTS.texture_cube_map_array.sampling.

v2: add 0.5 offset to tex coords only after derivative calculation
v3: go back to 1.5 offset

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:38:59 +01:00
Nicolai Hähnle
e01deee42f radeonsi: communicate cube map coordinates more explicitly
v2: fix compile error that snuck in during rebase

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-13 00:38:34 +01:00
Grazvydas Ignotas
c728051131 ac/debug: move .gitignore for sid_tables.h too
b838f642 "ac/debug: Move sid_tables.h generation to common code." moved
sid_tables.h but forgot the corresponding .gitignore.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-13 00:37:52 +01:00
Jason Ekstrand
08eced3cfd nir/gcm: Fix a typo in a comment
Reported-by: Matt Turner <mattst88@gmail.com>
2017-01-12 14:56:55 -08:00
Jason Ekstrand
087e172179 nir/gcm: Rework the schedule late loop
This fixes a bug in code motion that occurred when the best block is the
same as the schedule early block.  In this case, because we're checking
(lca != def->parent_instr->block) at the top of the loop, we never get to
the check for loop depth so we wouldn't move it out of the loop.  This
commit reworks the loop to be a simple for loop up the dominator chain and
we place the (lca != def->parent_instr->block) check at the end of the
loop.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-01-12 14:56:55 -08:00
Chuck Atkins
e9a4ec4bd8 glx: Add missing glproto dependency for gallium-xlib glx
Cc: mesa-stable@lists.freedesktop.org
Cc: Bruce Cherniak <bruce.cherniak@intel.com>
Signed-of-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-12 22:01:55 +00:00
Emil Velikov
c90f921273 ac, radeonsi: automake: add missing builddir include
The generated file is correctly stored in the builddir as of earlier
commit. Yet the commit forgot to add the respective include flag thus
the compiler would error out failing to find sid_tables.h

Bugzila: https://bugs.freedesktop.org/show_bug.cgi?id=99389
Fixes: d1dc22eb46 "ac: automake: rework sid_tables.h generation"
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-12 22:01:55 +00:00
Bas Nieuwenhuizen
8aaca3820c radv: Call NIR passes using NIR_PASS_V.
Port of faa1edeeb7
"anv/pipeline: Call NIR passes using NIR_PASS_V"

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2017-01-12 21:39:52 +01:00
Bas Nieuwenhuizen
65cbb993d3 radv: Call nir_lower_constant_initializers.
Port of c5d664f9dc
"anv/pipeline: Call nir_lower_constant_initializers"

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2017-01-12 21:39:46 +01:00
Bas Nieuwenhuizen
18e70edd8c radv: Only call remove_dead_variables once.
Port of 43e0b0d4b2
"anv/pipeline: Only call remove_dead_variables once"

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2017-01-12 21:39:41 +01:00
Axel Davy
970556292b st/nine: Protect dtors with mutex
When the flag D3DCREATE_MULTITHREAD is set, a global mutex is used
to protect nine calls.
However for performance reasons, AddRef and Release didn't hold the mutex,
and instead used atomics.

Unfortunately at item release, the item can be destroyed, and that
destruction path should be protected by a mutex (at least for
some objects).

Without this patch, it is possible an app thread is in a dtor
while another thread is making gallium nine calls. It is possible
that two threads are using the same gallium pipe, which is forbiden.
The problem has been made worse with csmt, because it can cause hang,
since nine_csmt_process is not threadsafe.

Fixes Hitman hang, and possibly others.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2017-01-12 20:33:11 +01:00
Axel Davy
5f4359ea0e st/nine: Flush the queue at device dtor
Flush the queue to get refcounts right, and properly
release the items, instead of throwing away all pending
commands.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2017-01-12 20:33:11 +01:00
Axel Davy
4e922c81f6 st/nine: Process pending commands on Reset
Some nine_state_* and nine_context_* functions
used for Reset() require all pending commands are
flushed.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2017-01-12 20:33:11 +01:00