Commit graph

9501 commits

Author SHA1 Message Date
Alyssa Rosenzweig
e7bb53467b intel: Produce unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
2023-05-16 22:36:21 +00:00
Lionel Landwerlin
ec4619a5e9 intel/devinfo: call intel_device_info_init_was only once
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8958

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22862>
2023-05-16 19:32:41 +00:00
Lionel Landwerlin
9ebd553fc2 intel/devinfo: allow -p to take a pci-id in hexa
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22862>
2023-05-16 19:32:41 +00:00
Lionel Landwerlin
fce55ffb7d intel/devinfo: printout on stdout
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22862>
2023-05-16 19:32:41 +00:00
Iván Briano
a15bffe2b8 anv: enable the GPL feature based on whether the extension is supported
Instead of checking if the very same bit we want to enable is already
enabled, which obviously doesn't work.

Fixes: fbc0e74bda ("anv: enable graphics pipeline libraries by default")

Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23039>
2023-05-16 02:01:30 +00:00
Nanley Chery
f220f3fdae intel/blorp: Assert an 8bpp fast clear restriction
We can't do fast clear operations on some LODs of 8bpp surfaces. Add an
assertion to BLORP to protect against drivers attempting to do this.

This assertion was successfully hit with some local modifications to
iris and with the piglit test case, "generatemipmap-base-change format".

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7301
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22857>
2023-05-15 19:54:02 +00:00
Zhang, Jianxun
7f84eee3c6 intel/isl: Fix map between sRGB and linear formats
Some SRGB formats don't get the expected linear counterparts in
isl_format_srgb_to_linear() in the generated isl_format_layout.c.

The replace() of string in python returns the unchanged input
string when no replacement occurred, so the first rule
('_SRGB', '') returns the original SRGB format name that passes
the following check unintendedly.

Another quirk is needed for a pair of formats not following
the patterns of other formats.

Signed-off-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22247>
2023-05-15 18:49:13 +00:00
Lionel Landwerlin
952a523abb intel: switch over to unified atomics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23004>
2023-05-15 16:32:21 +00:00
Konstantin Seurer
0cf22f9af3 nir: Make rq_load committed src an index
committed has to be a constant so there is no need to have a src and
depend on constant folding to remove the i2b.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>
2023-05-14 17:28:40 +00:00
Felix DeGrood
142c4f5abc intel: Secondary CB print primary CB's renderpass
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
2023-05-12 21:15:09 +00:00
Felix DeGrood
07ec481cd8 intel: batch consecutive dispatches into implicit renderpasses
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
2023-05-12 21:15:09 +00:00
Felix DeGrood
82f6a477f3 intel: refactor INTEL_MEASURE pointer dumping
Refactor framebuffer to renderpass to mirror previous INTEL_MEASURE
changes.

We dump hashes/pointers for shaders and framebuffer/renderpass.
Reduce from 64bit to 32bit pointers. We don't benefit from the
extra precision and reduced output size is convenient.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
2023-05-12 21:15:09 +00:00
Felix DeGrood
e2dfab5c96 anv: re-enable RT data in INTEL_MEASURE
Per-RenderTarget analysis was removed from anv's INTEL_MEASURE
previously, probably after switching to dynamic rendering model.
Restore capability by tracking count of beginRenderPass calls.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
2023-05-12 21:15:09 +00:00
Felix DeGrood
f783f581a8 anv: fix INTEL_MEASURE on MTL
Ensure counter buffer is coherent. Required for MTL which changes
coherence policy.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
2023-05-12 21:15:09 +00:00
Tapani Pälli
b0b6811b9b anv: handle missing astc for gfx125 in CreateImageView
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22818>
2023-05-12 06:59:34 +00:00
Iván Briano
d41b83e1ca hasvk: avoid assert due to unsupported format
Fixes: 0a4c92b646 ("hasvk: Use the common vk_ycbcr_conversion object")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9011
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22978>
2023-05-11 19:48:39 -07:00
Nanley Chery
e930ad6017 anv: Enable MCS init with ISL_AUX_OP_AMBIGUATE
Up until now, we have been initializing MCS with fast clears. This is
mostly safe, but there's a corner case that can be an issue.

The issue is with a workaround for MCS that requires the sampler not see
any fast-cleared blocks for certain surfaces (14013111325). Even though
we have been initializing MCS with fast clears, we expect most
applications to be safe because we expect that they would only sample
the samples they've rendered to previously (and the render would've
removed the fast-cleared blocks). In other words we don't expect that
apps would transition from VK_IMAGE_LAYOUT_UNDEFINED to
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL and start sampling immediately.

If an application took the unexpected path of sampling undefined
samples, it's possible they'd hit the issue described in the workaround.

Fix this corner case by using an ambiguate to initialize MCS.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
2023-05-11 23:41:16 +00:00
Nanley Chery
5b01a0ac47 anv: Drop the MCS initialization performance warning
The comment above the warning explains that not all bit patterns are
necessarily valid. While we're at it, fix a typo in that comment.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
2023-05-11 23:41:16 +00:00
Nanley Chery
bba4d850c2 intel: Implement ISL_AUX_OP_AMBIGUATE for MCS
Implement the ambiguate operation for MCS. This clears MCS layers with a
sample-dependent "uncompressed" value that tells the sampler to go look
at the main surface.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
2023-05-11 23:41:16 +00:00
Nanley Chery
a1ed41dec7 intel/isl: Bump the MCS halign value for BDW+
Select a horizontal alignment value that matches the main MSAA surface.

We need a valid horizontal alignment to perform MCS ambiguates. The
halign value doesn't actually affect test behavior, but it is validated
by isl_surf_fill_state. We currently have an invalid halign for gfx125.
This patch fixes that.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
2023-05-11 23:41:16 +00:00
Matt Turner
435a607909 intel: Disable shader cache when executing intel_clc during the build
With the shader cache enabled, intel_clc attempts to write to ~/.cache.
Many distributions' build systems limit file-system access, and will
kill the process thus causing the build to fail.

Fixes: 639665053f ("anv/grl: Build OpenCL kernels")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22968>
2023-05-11 23:00:01 +00:00
Chia-I Wu
eaf1776586 anv,hasvk: android ahb is not always exportable
anv_ahb_format_for_vk_format needs to know the format at least.  There
is no guarantee that AHardwareBuffer_allocate will succeed, but we are
reluctant to check with AHardwareBuffer_isSupported which may
test-allocate internally and is expensive.

v2: add anv_ahb_format_for_vk_format to anv_android_stubs.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:03 +00:00
Chia-I Wu
47b37651f8 vulkan: add vk_image_format_to_ahb_format
There should be no functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:03 +00:00
Chia-I Wu
380180516c anv,hasvk,radv: do not fall back to AHARDWAREBUFFER_FORMAT_BLOB
When allocating a VkDeviceMemory exportable as AHB, it seems incorrect
to fall back to AHARDWAREBUFFER_FORMAT_BLOB when the image has no known
AHB format.  We should fail the allocation instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:03 +00:00
Chia-I Wu
50e703f347 vulkan: add vk_ahb_format_to_image_format
There should be no functional change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Chia-I Wu
2bbe0462e8 vulkan: define inline stubs when android api level < 26
This allows us to reduce ANDROID #ifdef's.

v2: always include vk_android.h in radv_formats.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Chia-I Wu
f81dce9bcc vulkan: rename vk_image::ahardware_buffer_format
Rename it to ahb_format.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Chia-I Wu
5561abcb2c vulkan: make sure vk_image_view::format is never UNDEFINED
Remove redundant override in anv and hasvk as well.

Fixed
android.graphics.cts.BasicVulkanGpuTest#testBasicBufferImportAndRenderingExternalFormat
for radv.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Chia-I Wu
df8ec99c81 vulkan: make sure vk_image::format is never UNDEFINED
vk_image::android_external_format is only used for sanity check and is
removed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Chia-I Wu
0a4c92b646 hasvk: Use the common vk_ycbcr_conversion object
Based on commit 30a91d333d ("anv: Use the common vk_ycbcr_conversion
object").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Chia-I Wu
cb6d655f53 hasvk/android: Use VkFormat for externalFormat
Same as commit 18feb32df0 ("anv/android: Use VkFormat for
externalFormat"), but for hasvk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Chia-I Wu
6039f2a22f hasvk: Refactor Android externalFormat handling in CreateYcbcrConversion
Same as commit 9fc046a87d ("anv: Refactor Android externalFormat
handling in CreateYcbcrConversion"), but for hasvk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
2023-05-11 22:18:02 +00:00
Lionel Landwerlin
c61eea2ff3 intel/mi_builder: fixup tests for newer kernel uAPI
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22966>
2023-05-11 19:15:06 +00:00
José Roberto de Souza
4d4b0dfdb8 anv: Set memory types supported by Xe KMD
Due the lack of APIs to set mmap modes, Xe KMD can't support the same
memory types as i915.
So here adding a i915 and Xe function to set memory types supported
by each KMD.

Iris function iris_xe_bo_flags_to_mmap_mode() has a table with all the
mmaps modes of each type of placement.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22906>
2023-05-11 18:28:11 +00:00
Lionel Landwerlin
7381405095 anv: fixup workaround 16011411144
We're missing it for the memcpy with streamout

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5cc4075f95 ("anv, iris: Add Wa_16011411144 for DG2")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22930>
2023-05-11 15:24:03 +03:00
Daniel Schürmann
d3f06cf5ce vulkan/pipeline_cache: don't log warnings for internal caches
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22850>
2023-05-11 08:36:12 +00:00
Lionel Landwerlin
b4b17f8aaa Revert "intel/compiler: make uses_pos_offset a tri-state"
This reverts commit 5489033fa8.

The problem I was trying to address is that we were programming the
3DSTATE_PS::PositionXYOffsetSelect bit differently with GPL (CENTROID)
than without (NONE).

I failed to understand that this bit also impacts the thread payload
layout. GPL fragment shaders don't know ahead of time if pos_offset is
going to be used. It'll be choosen at runtime base on push constant
bits. So we need to program this bit different just to have a payload
matching the compiled shader code.

This fixes the freedoom replay with GPL FS shader in SIMD32.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22938>
2023-05-11 08:01:46 +00:00
Yiwei Zhang
b2d636b275 anv: apply ANV_BO_ALLOC_IMPLICIT_SYNC for external memory
This is necessary to make anv work with clients like VA-API which relies
on implicit fencing only. The bahavior matches iris i915_batch_submit.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22937>
2023-05-10 14:33:53 +00:00
Iván Briano
fbc0e74bda anv: enable graphics pipeline libraries by default
Since we are disabling mesh, which has issues with gpl, enable gpl by
default now, leaving the renamed environment variable as a way to
disable it for debug purposes.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22910>
2023-05-10 01:23:16 +00:00
Iván Briano
c97b1eb08a anv: put EXT_mesh_shader behind an environment variable
We are seeing frequent hangs in other workloads when something using
mesh shaders runs at the same time, so gate the feature behind an
environment variable until we figure out what's going on.

v2: (Sagar)
 - Give the mesh enabled variable a more descriptive name

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22910>
2023-05-10 01:23:16 +00:00
Rohan Garg
27b019d94e hasvk: drop dead code
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22830>
2023-05-09 10:22:10 +02:00
Rohan Garg
1896b48f4e anv: use the workaround framework for WA 14013111325
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22830>
2023-05-09 10:22:02 +02:00
Kenneth Graunke
f00143acc3 intel/compiler: Fold constants after distributing source modifiers
This can generate things like fneg! of load_const, which is silly.
Fold those away into an actual constant.  Only do so on the scalar
backend because there's a comment above that the vec4 backend doesn't
want any new constants this late, and I'm inclined to believe it.

fossil-db stats show a very minor improvement:

   Totals:
   Instrs: 203091223 -> 203091099 (-0.00%); split: -0.00%, +0.00%
   Cycles: 14410638075 -> 14410577067 (-0.00%); split: -0.00%, +0.00%

   Totals from 20 (0.00% of 665070) affected shaders:
   Instrs: 27067 -> 26943 (-0.46%); split: -0.47%, +0.01%
   Cycles: 2687958 -> 2626950 (-2.27%); split: -2.27%, +0.00%

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22881>
2023-05-09 00:16:40 -07:00
Lionel Landwerlin
cb8a878b53 intel: enable protected context creation along with engines
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22898>
2023-05-08 20:40:20 +00:00
Christopher Snowhill
a6d4139e59 Corrects log print to produce hexadecimal base output
Matching the original %016lx, and the "0x" prefix which is still
in the format string.

Fixes: 53b77a8102 ("anv: remove 48bit address space checks")

Signed-off-by: Christopher Snowhill <kode54@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22882>
2023-05-07 21:33:18 +00:00
Lionel Landwerlin
fb13360546 intel/fs: reduce register usage for relocated constants
Commit bb8e31b7ed ("anv: avoid hardcoding instruction VA constant in
shaders") had a slight negative impact on shaders (Red Dead Redemption
2 in particular). Dropping a few shaders from SIMD32 to SIMD16.

With this change, it brings back all the dropped SIMD32 shaders.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22872>
2023-05-07 19:38:04 +00:00
Marcin Ślusarz
d6ece34418 intel/tools: decode ACTHD printed by newer kernels
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22874>
2023-05-05 14:55:41 +00:00
Lionel Landwerlin
e64f5f261e anv: increase instruction heap to 2Gb
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8917
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
2023-05-05 14:48:15 +03:00
Lionel Landwerlin
c60e94d61f anv: make internal address space allocation more dynamic
We're about to manipulate these pools and dealing with the fix address
ranges is painful.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
2023-05-05 14:48:15 +03:00
Lionel Landwerlin
843afd4c63 anv: link anv_bo to its VMA heap
We want to add more heaps in the future and so not having to do
address checks to find out in what heap to release a BO is convinient.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22847>
2023-05-05 14:48:15 +03:00