fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-29 05:50:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

anv: Set memory types supported by Xe KMD

Browse source 
Due the lack of APIs to set mmap modes, Xe KMD can't support the same
memory types as i915.
So here adding a i915 and Xe function to set memory types supported
by each KMD.

Iris function iris_xe_bo_flags_to_mmap_mode() has a table with all the
mmaps modes of each type of placement.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22906>
This commit is contained in:
José Roberto de Souza 2023-04-27 14:14:22 -07:00 • committed by Marge Bot
parent ffbbf23ef8
commit 4d4b0dfdb8
5 changed files with 151 additions and 79 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

92
src/intel/vulkan/anv_device.c
View file

@ -871,7 +871,6 @@ anv_update_meminfo(struct anv_physical_device *device, int fd)
device->vram_non_mappable.available = devinfo->mem.vram.unmappable.free;
}
static VkResult
anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
{
@ -913,65 +912,6 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
.is_local_mem = true,
};
}
device->memory.type_count = 3;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 1,
};
device->memory.types[2] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
/* This memory type either comes from heaps[0] if there is only
* mappable vram region, or from heaps[2] if there is both mappable &
* non-mappable vram regions.
*/
.heapIndex = device->vram_non_mappable.size > 0 ? 2 : 0,
};
} else if (device->info.has_llc) {
device->memory.heap_count = 1;
device->memory.heaps[0] = (struct anv_memory_heap) {
.size = device->sys.size,
.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
.is_local_mem = false,
};
/* Big core GPUs share LLC with the CPU and thus one memory type can be
* both cached and coherent at the same time.
*
* But some game engines can't handle single type well
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360#note_1719438
*
* The second memory type w/out HOST_CACHED_BIT will get write-combining.
* See anv_AllocateMemory()).
*
* The Intel Vulkan driver for Windows also advertises these memory types.
*/
device->memory.type_count = 3;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
.heapIndex = 0,
};
device->memory.types[2] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 0,
};
} else {
device->memory.heap_count = 1;
device->memory.heaps[0] = (struct anv_memory_heap) {
@ -979,27 +919,21 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
.flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
.is_local_mem = false,
};
/* The spec requires that we expose a host-visible, coherent memory
* type, but Atom GPUs don't share LLC. Thus we offer two memory types
* to give the application a choice between cached, but not coherent and
* coherent but uncached (WC though).
*/
device->memory.type_count = 2;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
.heapIndex = 0,
};
}
switch (device->info.kmd_type) {
case INTEL_KMD_TYPE_XE:
result = anv_xe_physical_device_init_memory_types(device);
break;
case INTEL_KMD_TYPE_I915:
default:
result = anv_i915_physical_device_init_memory_types(device);
break;
}
if (result != VK_SUCCESS)
return result;
for (unsigned i = 0; i < device->memory.type_count; i++) {
VkMemoryPropertyFlags props = device->memory.types[i].propertyFlags;
if ((props & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) &&

79
src/intel/vulkan/i915/anv_device.c
View file

@ -125,6 +125,85 @@ anv_i915_physical_device_get_parameters(struct anv_physical_device *device)
return result;
}
VkResult
anv_i915_physical_device_init_memory_types(struct anv_physical_device *device)
{
if (anv_physical_device_has_vram(device)) {
device->memory.type_count = 3;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 1,
};
device->memory.types[2] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
/* This memory type either comes from heaps[0] if there is only
* mappable vram region, or from heaps[2] if there is both mappable &
* non-mappable vram regions.
*/
.heapIndex = device->vram_non_mappable.size > 0 ? 2 : 0,
};
} else if (device->info.has_llc) {
/* Big core GPUs share LLC with the CPU and thus one memory type can be
* both cached and coherent at the same time.
*
* But some game engines can't handle single type well
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360#note_1719438
*
* The second memory type w/out HOST_CACHED_BIT will get write-combining.
* See anv_AllocateMemory()).
*
* The Intel Vulkan driver for Windows also advertises these memory types.
*/
device->memory.type_count = 3;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
.heapIndex = 0,
};
device->memory.types[2] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 0,
};
} else {
/* The spec requires that we expose a host-visible, coherent memory
* type, but Atom GPUs don't share LLC. Thus we offer two memory types
* to give the application a choice between cached, but not coherent and
* coherent but uncached (WC though).
*/
device->memory.type_count = 2;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
.heapIndex = 0,
};
}
return VK_SUCCESS;
}
VkResult
anv_i915_device_setup_context(struct anv_device *device,
const VkDeviceCreateInfo *pCreateInfo,

2
src/intel/vulkan/i915/anv_device.h
View file

@ -30,6 +30,8 @@ struct anv_physical_device;
VkResult
anv_i915_physical_device_get_parameters(struct anv_physical_device *device);
VkResult
anv_i915_physical_device_init_memory_types(struct anv_physical_device *device);
VkResult
anv_i915_device_setup_context(struct anv_device *device,

54
src/intel/vulkan/xe/anv_device.c
View file

@ -118,6 +118,60 @@ anv_xe_physical_device_get_parameters(struct anv_physical_device *device)
return VK_SUCCESS;
}
VkResult
anv_xe_physical_device_init_memory_types(struct anv_physical_device *device)
{
if (anv_physical_device_has_vram(device)) {
device->memory.type_count = 3;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 1,
};
device->memory.types[2] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
/* This memory type either comes from heaps[0] if there is only
* mappable vram region, or from heaps[2] if there is both mappable &
* non-mappable vram regions.
*/
.heapIndex = device->vram_non_mappable.size > 0 ? 2 : 0,
};
} else if (device->info.has_llc) {
/* Big core GPUs share LLC with the CPU and thus one memory type can be
* both cached and coherent at the same time.
*
* But some game engines can't handle single type well
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360#note_1719438
*
* TODO: But with current UAPI we can't change the mmap mode in Xe, so
* here only supporting two memory types.
*/
device->memory.type_count = 2;
device->memory.types[0] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
.heapIndex = 0,
};
device->memory.types[1] = (struct anv_memory_type) {
.propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
.heapIndex = 0,
};
} else {
return vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
"No memory heaps types set for non llc devices yet on Xe");
}
return VK_SUCCESS;
}
VkResult
anv_xe_device_check_status(struct vk_device *vk_device)
{

3
src/intel/vulkan/xe/anv_device.h
View file

@ -38,5 +38,8 @@ VkResult anv_xe_device_check_status(struct vk_device *vk_device);
VkResult
anv_xe_physical_device_get_parameters(struct anv_physical_device *device);
VkResult
anv_xe_physical_device_init_memory_types(struct anv_physical_device *device);
enum drm_sched_priority
anv_vk_priority_to_drm_sched_priority(VkQueueGlobalPriorityKHR vk_priority);