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Author SHA1 Message Date
Gert Wollny
e57643cf54 r600/sfn: Add handling for R600 indirect access alias handling 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
d955633319 r600/sfn: Add chip family to shader class 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
4d5859a524 r600/sfn: Start a new ALU CF on index use, not on index emission 
With that we can use the two IDX registers in parallel any might
save some CF instructions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
557dc14944 r600/sfn: set CF force flag always when starting a new block 
There is no reason not to do this, because we only start a new
block if a new CF block must be started.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
e9e1806a2e r600/sfn: Add test for multiple index load 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
669aba02b0 r600/sfn: Don't copy-propagate indirect access into LDS instr 
Propagating array elements has the problem that we would have to
check whether the last load is not overwritten by an indirect store.

Indirect kcache buffer loads require starting a new CF, and we would
have to make sure that we don't split the LDS fetch/read group with
that, so don't do this.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
f4816d2a72 r600/sfn: Add more tests and update to use address splits 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
d617052db6 r600/sfn: take address loads into account when scheduling 
Also change a bit the instruction priority handling

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
8e1cf2d439 r600/sfn: Add function to check whether a group loads a index register 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
d21054b4bc r600/sfn: Add pass to split addess and index register loads 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
aca80216c1 r600/sfn: Add interface to count AR uses in ALU op 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
6e5327fef6 r600/sfn: Add a RW get function of IF predicate access 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
a7611bc093 r600/sfn: AR and IDX don't need the write flag, but haev a parent 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
cb8f12ded5 r600/sfn: Be able to track expected AR uses 
Because AR emission and AR use must be in the same CF we have to
be able to track whether all AR ready are emitted.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
af3d496253 r600/sfn: Update resource based instruction index mode check 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
e7b497fe87 r600/sfn: Add function to insert op in block 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
f464fc28d4 r600/sfn: add method to update indirect address to all instrution types 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
c3f60f77d6 r600/sfn: handle AR and IDX register in shader from string 
This is needed for testing

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
9a29301567 r600/sfn: Prepare uniforms and local arrays for better address handling 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:55 +00:00
Gert Wollny
fac4760c7d r600: Allow both index registers for all CF types 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Gert Wollny
db0752a809 r600/sfn: don't allow more than one AR per instruction 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Gert Wollny
886a3e5286 r600/sfn: Rework query for indirect access in alu instr and opt 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Gert Wollny
5579263368 r600/sfn: Add address and index registers creation to ValueFactory 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Gert Wollny
a40c1c9d5c r600/sfn/tests: Cleanup and move some code around 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Gert Wollny
c5ea9182b4 r600/sfn: Handle MOVA_INT in sfn assembler 
To properly emit ALU clauses we have to make sure the backend doesn't
add instructions for the address emission.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Gert Wollny
077f7d25df r600/sfn: don't track address registers in live ranges 
There is only one address register, and for the index registers we
don't do a special register allocation, so no need to track these
either.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Gert Wollny
bd9b653dbb r600/sfn: Add a type for address registers 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
 2023-04-28 13:13:54 +00:00
Matt Coster
1c00dec60d pvr: Fully declare support for VK_EXT_private_data 
Fixes: dEQP-VK.api.info.get_physical_device_properties2.features
  .private_data_features

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22738>
 2023-04-28 10:52:22 +00:00
Karmjit Mahil
2de6bdd449 pvr: Fix static assert check 
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22595>
 2023-04-28 10:35:23 +00:00
Karmjit Mahil
a8f841dad9 pvr: Change push_constants_shader_stages to type pvr_stage_allocation 
Previously the code was saving the mask as a VkShaderStageFlags
but when allocating shareds it checked against pvr_stage_allocation.
This causes problems as only the vertex bit matches the
VkShaderStageFlagBits so the push constants utilized in fragment
shaders weren't picked up properly.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22731>
 2023-04-28 09:16:02 +00:00
Karmjit Mahil
c38da3dcd2 pvr: Fix pvr_csb_bake() list return. 
The list logic checks for list->next->next (+ some other checks)
to point to the list itself to determine that there is just one
single element.

 ┌───────────────────────┐
 └< { HEAD } >─< { E0 } >┘

When the list_head is copied as was being done previously, the
list element's next pointer still points at the old head so
the `list_is_singular()` check fails.

Fixes pvr_cmd_buffer.c:605:`list_is_singular(&bo_list)` assertion
dEQP-VK.api.image_g.core.clear_color_attachment.cube_layers.b8g8r8a8_unorm

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22730>
 2023-04-28 08:54:19 +00:00
Felix DeGrood
b22e5fab8c docs: Add INTEL_DEBUG_BATCH_FRAME_START/_STOP 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
 2023-04-28 04:37:05 +00:00
Felix DeGrood
543c554ed6 iris: Enable INTEL_DEBUG_BATCH_FRAME_START/_STOP 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
 2023-04-28 04:37:05 +00:00
Felix DeGrood
61c209095c anv: Enable INTEL_DEBUG_BATCH_FRAME_START/_STOP 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
 2023-04-28 04:37:05 +00:00
Felix DeGrood
015eecde47 intel/debug: Control start/stop frame of batch debug 
When using INTEL_DEBUG=bat, INTEL_DEBUG_BATCH_FRAME_START and
INTEL_DEBUG_BATCH_FRAME_STOP can limit dumping of batches for
particular frame ranges. Batch dumps are huge. Smart filtering
allows debugging of single frames during game play. Initial
commit to debug infrastructure.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
 2023-04-28 04:37:05 +00:00
Qiang Yu
65c3d1869d aco: allow no export instruction for gfx10+ fs 
radeonsi will generate no export instruction when no
discard and no output.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>
 2023-04-28 11:33:28 +08:00
Qiang Yu
3c59df7318 aco: get scratch addr from symbol for radeonsi 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>
 2023-04-28 11:33:28 +08:00
Qiang Yu
360176b671 aco,radv: support symbol relocation in aco 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>
 2023-04-28 11:33:28 +08:00
Jesse Natalie
3fc4ddd628 dzn: Expose core VK1.2 extensions that aren't optional 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22745>
 2023-04-28 00:03:17 +00:00
Jesse Natalie
0b8a39498d dzn: Expose core VK1.1 extensions that aren't optional 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22745>
 2023-04-28 00:03:17 +00:00
Lone_Wolf
a1b46b5e66 clc: Add clang frontendhlsl module to fix build of microsoft-clc with llvm 16+ 
Cc: mesa-stable

Reviewed-by: Jesse Natalie  <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>
 2023-04-27 23:06:42 +00:00
Lone_Wolf
d09a7132d8 clc: Add clangASTMatchers to fix static llvm build of microsoft-clc with LLVM 16+ 
Cc: mesa-stable

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>
 2023-04-27 23:06:42 +00:00
Lone_Wolf
f53e5efad7 compiler/clc: Fix embedded clang headers (microsoft-clc) for LLVM 16+ 
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7742

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>
 2023-04-27 23:06:42 +00:00
Eric Engestrom
6a08dc7cab v3d: fix tfu_supports_tex_format() param type, and document why 
tex_format should be `enum V3DX(Texture_Data_Formats)`, but using that enum
type in the header requires including `v3dx_pack.h`, which triggers circular
include dependencies issues, so use a `uint32_t` for now.

"fix" the one place that was using the correct enum, because doing so
triggers `-Wenum-int-mismatch` in GCC 13 as the function declaration
doesn't match the function definition.

Reported-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22739>
 2023-04-27 22:17:48 +00:00
Danylo Piliaiev
4dd15177d0 ir3: documents (ss) flag for cat7 instructions 
Blob produces "lock" instructions with (ss), so our past guess that
cat7 supports (ss) is true.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
 2023-04-27 21:06:47 +00:00
Mark Collins
85c6c9068a ir3/a7xx: Add definitions for (last) src GPR attribute 
A new attribute on source GPRs reflecting if a certain usage of a
value is the last usage of it was added in A7xx. This is seemingly
a performance hint and doesn't affect anything when not applied.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
 2023-04-27 21:06:47 +00:00
Danylo Piliaiev
1613d767c1 ir3/a7xx: Document "alias" instruction 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
 2023-04-27 21:06:47 +00:00
Danylo Piliaiev
b909eda0b3 ir3: Document that stc has higher DST upper bound than we defined 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
 2023-04-27 21:06:47 +00:00
Danylo Piliaiev
11b2c54a9a ir3/a7xx: Add STSC definition 
STore Shared Const - loads SIZE dwords from HLSQ_SHARED_CONSTS_IMM
starting from HLSQ_SHARED_CONSTS_IMM[SRC] and writing them to c[DST]

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
 2023-04-27 21:06:47 +00:00
Danylo Piliaiev
80f878b103 ir3/a7xx: Add new form of stg.a/ldg.a addressing 
The new stg.a/ldg.a addressing form supersedes the a6xx's one.

The new form is:
 ldg.a.f32 r4.y, g[c0.z+r4.y+2], 4

There are no shift comparing to the a6xx:
 ldg.a.f32 r4.y, g[r0.z+(r4.y)<<2], 4

Also on a7xx the first src is allowed to be both const and gpr.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
 2023-04-27 21:06:46 +00:00