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ir3: Document that stc has higher DST upper bound than we defined

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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
This commit is contained in:
Danylo Piliaiev 2023-02-22 19:34:54 +01:00 • committed by Marge Bot
parent 11b2c54a9a
commit b909eda0b3
2 changed files with 5 additions and 1 deletions
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3
src/freedreno/ir3/tests/disasm.c
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@ -240,6 +240,9 @@ static const struct test {
INSTR_6XX(c7020020_01800000, "stc.f32 c[32], r0.x, 1"), /* stc c[32], r0.x, 1 */
/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
INSTR_6XX(c7060020_03800000, "stc.u32 c[32], r0.x, 3"), /* stc c[32], r0.x, 3 */
/* A660 EQP-VK.robustness.robustness2.push.notemplate.r32i.unroll.nonvolatile.sampled_image.no_fmt_qual.img.samples_1.1d.frag */
/* TODO: stc has a similar to stsc DST range */
/* INSTR_6XX(c702026e_0480025c, "stc.u32 c[366], r11.z, 4"), */ /* stc c[366], r11.z, 4 */
/* dEQP-VK.pipeline.monolithic.extended_dynamic_state.two_draws_static.stencil_state_face_both_single_gt_replace_clear_102_ref_103_depthfail */
INSTR_7XX(c7420000_0cc00000, "stsc.f32 c[0], 0, 12"),

3
src/freedreno/isa/ir3-cat6.xml
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@ -445,7 +445,8 @@ SOFTWARE.
<gen min="600"/>
<pattern pos="0" >x</pattern>
<field low="1" high="8" name="SRC" type="#reg-gpr"/>
<pattern low="9" high="22">xxxxxxxxxxxxxx</pattern>
<pattern low="9" high="13">xxxxx</pattern> <!-- DST_HI -->
<pattern low="14" high="22">xxxxxxxxxxxxxx</pattern>
<pattern pos="23" >1</pattern>
<field low="24" high="26" name="SIZE" type="uint"/>
<pattern low="27" high="31">xxxxx</pattern>