Commit graph

188610 commits

Author SHA1 Message Date
Erik Faye-Lund
dd3ee08b05 docs/panfrost: link to conformant products
Let's link to the conformant products page on the Khronos' website, in
case someone wants to look at some of the details of the submissions.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28968>
2024-04-30 13:19:49 +00:00
Connor Abbott
fe4ebace79 ir3: Don't manually scalarize SSBO loads
We call nir_lower_io_to_scalar already, so this should be dead code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28949>
2024-04-30 12:01:52 +00:00
Connor Abbott
cd15dec66e ir3: Don't scalarize all SSBO instructions
Use the newly-introduced filter to only scalarize the instructions we
need to scalarize.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28949>
2024-04-30 12:01:52 +00:00
Samuel Pitoiset
86281ef15f radv: add shaders BO to the cmdbuf BO list at bind time
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Samuel Pitoiset
42554e81b9 radv: add RT prolog BO to the cmdbuf BO list at bind time
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Samuel Pitoiset
42dc4b463b radv: add GS copy shader BO to the cmdbuf BO list at bind time
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Samuel Pitoiset
2664e058de radv: use the bound GS copy shader when emitting shader objects
Similar but doesn't rely on shader_objs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Samuel Pitoiset
be98fe2724 radv: pre-compute VGT_TF_PARAM.DISTRIBUTION_MODE
For less CPU overhead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Samuel Pitoiset
d7679c0370 radv: remove useless DB_Z_INFO.NUM_SAMPLES when emitting the MSAA state
DB_Z_INFO.NUM_SAMPLES is now correctly set when a null framebuffer is
emitted and this is redundant.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Samuel Pitoiset
4dd682e227 radv: inline radv_get_pa_su_sc_mode_cntl() in radv_emit_culling()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Samuel Pitoiset
e651a2c856 radv: simplify radv_emit_primitive_restart_enable()
Move emitting VGT_MULTI_PRIM_IB_RESET_INDX into the GFX6-8 branch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28965>
2024-04-30 07:18:08 +00:00
Christian Gmeiner
d1e5b13359 mr-label-maker: Add teflon marker
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28959>
2024-04-30 07:13:18 +00:00
Marek Olšák
8416ba9c25 amd/ci: 17 piglit failures are fixed for raven
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:21 +00:00
Marek Olšák
98e976dcdb radeonsi: check for FMASK correctly in gfx10_get_bin_sizes
so that this code is skipped on gfx11+

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:21 +00:00
Marek Olšák
1a3c5cf17b radeonsi: enable DCC for MSAA on gfx10-10.3
It improves performance of the MSAA resolving tests.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:21 +00:00
Marek Olšák
eb7d747651 radeonsi: add workarounds for DCC MSAA for gfx9-10
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:21 +00:00
Marek Olšák
1929bb0d8d radeonsi: validate IO semantics in scan_io_usage
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:21 +00:00
Marek Olšák
cfe197e61c radeonsi: fix KHR-GL46.texture_lod_bias.texture_lod_bias_all on gfx10-11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:20 +00:00
Marek Olšák
6f09751548 radeonsi: don't invalidate L2 for internal compute without DCC stores
When internal compute shaders are used, existing shader images are not
fully unbound, which means any image can be bound, even if the internal
shader doesn't use images.

This strengthens the code by applying it only to images used by internal
compute shaders.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:20 +00:00
Marek Olšák
c87ce78d10 ac/surface: enable thick tiling for 3D textures for better perf on gfx6-8
This increases performance 2.5x for Viewperf/Energy on Tonga.
The value of thick_tiling is also fixed.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:20 +00:00
Marek Olšák
33f642aa09 ac/surface: disable DCC for 3D textures on gfx9 to improve performance
This improves Viewperf/Energy perf by 60% on Vega10.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:20 +00:00
Marek Olšák
e05aec3fcd ac/gpu_info: set tcc_rb_non_coherent only if number of TCCs != number of RBs
This sets it to false for Navi31 to eliminate unnecessary L2 cache
invalidations.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28846>
2024-04-30 06:47:20 +00:00
Iago Toral Quiroga
027c01bd8f v3d,v3dv: stop hard-coding max attrib divisor
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28964>
2024-04-30 06:27:21 +00:00
Iago Toral Quiroga
e8f96dd0b0 v3dv: fix VK_KHR_vertex_attribute_divisor
When this was promoted to EXT it expanded its properties struct to add a new
supportsNonZeroFirstInstance field.

Fixes: d38ff02c03 ("v3dv: mark some promoted extensions as supported")
Fixes: dEQP-VK.api.info.vulkan1p2_limits_validation.khr_vertex_attribute_divisor

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28964>
2024-04-30 06:27:21 +00:00
Patrick Lerda
fe8fdc58db gallium/auxiliary/vl: fix typo which negatively impacts the src_stride initialization
Note: As a matter of fact, this change by itself makes vdpau on r600 works again.
Indeed, r600 sets the stride value with vertex_buffer_index as the r600 index;
vertex_buffer_index was set to zero at the vl_compositor/init_buffers() stage on
the three elements. As a consequence of this typo the stride value was overwritten
to zero. This was breaking vdpau.

Fixes: 76725452 ("gallium: move vertex stride to CSO")
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10468
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10267
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28966>
2024-04-30 05:45:21 +00:00
Martin Krastev
3daee9b677 svga: update timespan in copyright message
Update copyright timespans to include 2024.

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28647>
2024-04-30 03:36:16 +00:00
Martin Krastev
901269955d svga: convert license block to SPDX
* adopt a simplified SPDX scheme -- drop inline licenses
* switch copyright from VMware to Broadcom

Signed-off-by: Martin Krastev <martin.krastev@broadcom.com>
Reviewed-by: Jose Fonseca <jose.fonseca@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28647>
2024-04-30 03:36:16 +00:00
Mike Blumenkrantz
ad39355e83 kopper: don't set drawable buffer age
this is broken

Fixes: 2a8c6cf7ac ("kopper: set drawable buffer age")

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28904>
2024-04-29 23:08:11 +00:00
Mike Blumenkrantz
19e8df39b6 zink: slightly better swapinterval failure handling
retain the old mode and print an error

cc: mesa-stable

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28904>
2024-04-29 23:08:11 +00:00
Mike Blumenkrantz
a50c17802a kopper: fix bufferage/swapinterval handling for non-window swapchains
if swapchain creation fails (e.g., insane cts swapchain configs), the
swapchain gets demoted to a non-window image that is still accessed by
the frontend. this image should not ever hit corresponding zink entrypoints
for swapchain-only images, which requires a flag to test swapchain-edness

cc: mesa-stable

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28904>
2024-04-29 23:08:11 +00:00
JCWasmx86
7352f948be meson: Fix invalid kwarg name
Introduced in !28576

Fixes:  44b080af ("meson: implement split-debug")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28924>
2024-04-29 20:52:12 +00:00
Erik Faye-Lund
8248cc0bf4 docs/panfrost: move details to separate articles
The front-page of the docs is currently fairly intimidating, by diving
into details rather abruptly. Let's try to make it a bit easier to
navigate t by moving the details to their own articles, but linking them
from the front-page.

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28953>
2024-04-29 13:24:51 +00:00
Erik Faye-Lund
da2cc20714 docs/panfrost: compact gpu-table
This table is getting long and terse, let's compact it a bit.

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28953>
2024-04-29 13:24:51 +00:00
Christian Gmeiner
2cb8e9a856 etnaviv: isa: Add name for full writemask
Is needed to generate a nicer code.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:28 +00:00
Christian Gmeiner
cb69595037 etnaviv: isa: Rework modeling of left shift for store/load
This makes is easier for the parser to process.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner
f8c38ec648 etnaviv: isa: Add more flags to etna_inst
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner
a0dad2e705 etnaviv: isa: Switch to enum isa_thread
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner
87e5ad3930 etnaviv: isa: Print dst_full for ALU
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
Christian Gmeiner
0c70dcd6f7 etnaviv: isa: Add clang-format special comments
We want to keep the defines as formated as they are.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28929>
2024-04-29 13:02:27 +00:00
David Rosca
bc72126cb4 radeonsi/vcn: Only enable VBAQ with rate control mode
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10020
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28945>
2024-04-29 12:38:33 +00:00
David Rosca
b144f50190 radeonsi/vcn: Fix 10bit HEVC VPS general_profile_compatibility_flags
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28945>
2024-04-29 12:38:33 +00:00
David Rosca
cc0df497f0 radeonsi/vcn: Allocate session buffer in VRAM
It's never mapped so there's no reason for PIPE_USAGE_STAGING.
Improves encoding performance on dGPUs.

Tested with 7900XTX (before 1900fps => after 2100fps):

  ffmpeg -hide_banner -hwaccel vaapi -hwaccel_device /dev/dri/renderD128 \
  -f lavfi -i testsrc=size=640x640,format=nv12 -vf hwupload -c:v av1_vaapi \
  -f null -

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28945>
2024-04-29 12:38:33 +00:00
Samuel Pitoiset
0b51868193 radv: remove bogus VkShaderCreateInfoEXT::flags being 0 assert for compute
This was a leftover. Flags can be different than 0, like for required
subgroup size and it should already be correctly supported.

Fixes recent dEQP-VK.shader_object.performance.dispatch_base.

Fixes: 37d7c2172b ("radv: add support for creating/destroying shader objects")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28946>
2024-04-29 11:45:03 +00:00
Christian Gmeiner
8c2a749f67 etnaviv: isa: Drop capturing of python output
Is nicer for meson.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28875>
2024-04-29 11:26:03 +00:00
Samuel Pitoiset
85deb9f706 radv: simplify DB_Z_INFO.NUM_SAMPLES with null ds target on GFX11
According to PAL, the hw uses the smaller value of
DB_Z_INFO.NUM_SAMPLES and PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES when
there is no bound depth/stencil buffer, and it uses 8x to make sure
the used value is MSAA_EXPOSED_SAMPLES.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28952>
2024-04-29 11:02:02 +00:00
Eric Engestrom
45edd99b6b ci: mark microsoft farm as offline
It's having issues right now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28967>
2024-04-29 12:53:51 +02:00
Kenneth Graunke
674e89953f intel/brw: Use new builder helpers that allocate a VGRF destination
With the previous commit, we now have new builder helpers that will
allocate a temporary destination for us.  So we can eliminate a lot
of the temporary naming and declarations, and build up expressions.

In a number of cases here, the code was confusingly mixing D-type
addresses with UD-immediates, or expecting a UD destination.  But the
underlying values should always be positive anyway.  To accomodate the
type inference restriction that the base types much match, we switch
these over to be purely UD calculations.  It's cleaner to do so anyway.

Compared to the old code, this may in some cases allocate additional
temporary registers for subexpressions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Kenneth Graunke
4c2c49f7bc intel/brw: Add builder helpers that allocate temporary destinations
In many cases, we calculate an expression by generating a series of
instructions.  We'd either overwrite the same register repeatedly,
or call vgrf(BRW_TYPE_X) repeatedly to allocate temporaries for each
intermediate step.  In many cases, we overwrote the same register simply
because allocating and naming temporaries for each step was annoying.

This commit adds new builder helpers that will allocate a temporary
destination for you, using simple type interference: unary operations
use the source type, and binary operations require a matching base type
and return the largest of the two types.

The helpers return the destination register, allowing us to write in an
expression-tree style, chaining together builder operations to produce
whole values.  Sort of like nir_builder.  We still optionally will write
out the fs_inst pointer in case the caller wants to do things like set
predicates or saturation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Kenneth Graunke
319ba85e10 intel/brw: Add builder helpers for math functions
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00
Kenneth Graunke
cf8ed9925f intel/brw: Make a helper for finding the largest of two types
Some instructions can operate on mixed types.  Typically this is
something like a binary operation with UD and UW sources resulting
in a UD destination.  In order to make it easier to find the result
type of such operations, let's make a type helper that returns the
larger of the two types (but requires the base type to match).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957>
2024-04-29 07:51:45 +00:00