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Author SHA1 Message Date
Timur Kristóf
dc6ae1855a ac/nir/ngg: Use gfx_level from radeon_info. 
So we don't have to pass it separately.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:46 +00:00
Timur Kristóf
e1be943f10 ac/nir/ngg: Add and use a has_ngg_passthru_no_msg field to ac_gpu_info. 
Instead of using the chip family field.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
a40000b85b ac/nir/ngg: Add and use a has_ngg_fully_culled_bug field to ac_gpu_info. 
Better than applying the workaround ad-hoc based on GFX level.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
cad0d26dbf ac/nir/ngg: Add and use a has_attr_ring field to ac_gpu_info. 
While theoretically all GFX11+ GPUs have an attribute ring, it is
nicer to have this property instead of deciding ad-hoc based on
the GFX level.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
b163ce51b1 ac/nir/ngg: Add and use a has_attr_ring_wait_bug field to ac_gpu_info. 
And apply the attribute ring wait workaround based on the new field.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
e76361d626 ac/nir/ngg: Add radeon_info to NGG lowering options. 
The intention is to have all the HW features affecting
shader compilation in one place, instead of ad-hoc decisions
in the code based on the GFX level and chip class.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
28c501f22c ac/nir/ngg: Slightly refactor emitting vertex parameters. 
No functional changes, just some code cleanup.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
9860fb3780 ac/nir/ngg: Carve out ac_nir_repack_invocations_in_workgroup. 
We're going to want to call it from a different	file too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
d2ff3f9fa0 ac/nir/ngg: Carve out NGG streamout code. 
We're going to want to call it from a different	file too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
1d8f46e00c ac/nir/ngg: Carve out ac_nir_create_output_phis. 
We're going to want to call it from a different	file too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
4bec453595 ac/nir/ngg: Use ac_nir_ngg_alloc_vertices_and_primitives in mesh shader lowering. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
02dacac869 ac/nir/ngg: Carve out ac_nir_ngg_alloc_vertices_and_primitives. 
We're going to want to call it from a different file too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
a3d8e6a60c ac/nir/ngg: Remove unused vs_output struct. 
Forgot to remove this when I refactored the code to use
ac_nir_prerast_out instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
23641d4032 ac/nir/ngg: Add a few comments explaining some variables. 
These were somewhat confusing, so let's add a few words to
explain what they are exactly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
28f49bf99c ac/nir/ngg: Remove some superfluous variables from culling code. 
No functional changes, just code cleanup.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
e9069eec8a aco: Move NGG pos export scheduling determination to drivers. 
And don't schedule them on GFX11+ at all.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
7a3d95bbe2 ac/nir/ngg: Mitigate attribute ring wait bug when primitive ID is per-primitive. 
There is a possibility that some waves in an NGG workgroup
don't have any input vertices, only primitives. When these
waves store the primitive ID as a per-primitive attribute,
they will need to wait for those stores before the primitive
export, because the other waves can't wait for them.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Timur Kristóf
397d45d055 ac/nir/ngg: Mitigate NGG fully culled bug when GS output is compile-time zero. 
This case is unlikely but possible. We forgot to handle it here,
because it was originally handled by the backend compiler.

On GFX10 chips that have issues with 0 vertices and primitives
exported, this will always export at least 1 vertex and primitive.

This could theoretically fix some hangs on Navi 10, although we are not aware of a specific issue caused by this problem.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
 2025-01-30 15:26:45 +00:00
Valentine Burley
06ab1c81d1 amd/ci: Increase amd-raven-skqp parallelism 
This job was taking too long and there's more DUTs in available in LAVA.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Eric Engestrom <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33298>
 2025-01-30 10:25:05 +00:00
Mike Blumenkrantz
d8b7fbd4ac ci: mark radv-raven-traces-restricted with allow_failure 
restricted trace jobs are allowed to fail

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33244>
 2025-01-30 09:49:11 +00:00
Samuel Pitoiset
d6f9c19755 radv/amdgpu: add support for AMDGPU_GEM_CREATE_GFX12_DCC 
This flags will be used to set PTE.DCC to VRAM allocations
(ie. compression).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33284>
 2025-01-30 08:18:22 +00:00
Samuel Pitoiset
5ac72c5f56 ac/descriptors: allow to configure DCC for buffer descriptors 
This is not used yet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33284>
 2025-01-30 08:18:22 +00:00
Samuel Pitoiset
fe6494559d ac,radeonsi: add SDMA DCC tiling for GFX12+ 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33284>
 2025-01-30 08:18:22 +00:00
Daniel Schürmann
65f95ae74e aco/insert_NOPs: implement VALU -> VALU case for VALUReadSGPRHazard on GFX12 
Totals from 36918 (46.50% of 79395) affected shaders: (GFX1200)

Instrs: 34997889 -> 35296429 (+0.85%); split: -0.00%, +0.85%
CodeSize: 186161112 -> 187334364 (+0.63%); split: -0.00%, +0.63%
Latency: 250265551 -> 250330784 (+0.03%); split: -0.00%, +0.03%
InvThroughput: 41185298 -> 41192503 (+0.02%); split: -0.00%, +0.02%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32682>
 2025-01-30 03:13:16 +00:00
Daniel Schürmann
6c7355f0e6 aco/insert_NOPs: refactor VALUReadSGPRHazard detection 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32682>
 2025-01-30 03:13:16 +00:00
Valentine Burley
098c81d663 amd/ci: Migrate amd-raven-skqp from lenovo-zork to hp-zork 
We have more hp-x360-14a-cb0001xx-zork DUTs available in LAVA,
use it to offload the overloaded lenovo-TPad-C13-Yoga-zork.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33082>
 2025-01-29 20:34:14 +00:00
Timur Kristóf
8b263555ee radv: Lower array derefs of vectors outside of shader linking. 
This fixes depth-only rendering with mesh shaders,
as well as array derefs in unlinked shaders in general.

Lowering array derefs of vectors is necessary for correctness.
Without this, nir_lower_io will incorrectly add the array index
to the IO intrinsic base instead of to the component offset.

This was previously only done during shader linking, which leaves
some problems with unlinked shaders and depth-only rendering.

Whether these calls can be safely removed from shader linking
will be investigated in a future commit.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12516
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33264>
 2025-01-29 20:05:25 +00:00
Samuel Pitoiset
4425d8556f radv: use stage instead of entrypoint to determine valid gfx stages 
Otherwise if the function name is stripped during NIR serialization,
importing libraries would break because entrypoint is NULL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33273>
 2025-01-29 14:37:41 +00:00
Samuel Pitoiset
e77a409b26 radv/ci: add expected list of failures for GFX1200 
Same as NAVI31.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33258>
 2025-01-29 08:31:10 +00:00
Marek Olšák
d0e1c508c6 ac/fake_hw_db: deobfuscate GPU name strings 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
 2025-01-29 07:20:02 +00:00
Marek Olšák
43588be435 radeonsi: remove an incorrectly defined modifier 
It's missing the PACKERS field to distinguish between different layouts
and it's a useless swizzle mode anyway.

Fixes: 0833dd7d12 - amd/common: Add support for modifiers.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9344

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
 2025-01-29 07:20:01 +00:00
Marek Olšák
71e95b373b radeonsi: remove si_shader_info code that is no longer needed 
A lot of this info is now derived from shader variant NIR.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
 2025-01-29 07:19:56 +00:00
Marek Olšák
8e8eda4089 radeonsi: fix PS prolog not counting used fragcoord VGPRs correctly 
Using the used component count is not enough. We need to consider
the component mask because any component can be disabled. This might
fix tests.

This removes the component counting from ac_get_fs_input_vgpr_cnt
and determines the component mask where it's needed.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
 2025-01-29 07:19:40 +00:00
Marek Olšák
b3fc49686e ac/nir: clamp vertex color outputs in the right place 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
 2025-01-29 07:19:38 +00:00
Samuel Pitoiset
18c7eafcdc radv: fix programming mip level for TILED_SUB_WINDOWS on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33252>
 2025-01-28 20:32:11 +00:00
Samuel Pitoiset
7c949f1760 radv: fix programming pitches for LINEAR_SUB_WINDOW on GFX12 
GFX12 supports up to 64k images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33252>
 2025-01-28 20:32:11 +00:00
Georg Lehmann
b23ff87db4 aco/sched_ilp: base latency and issue cycles on aco_statistics 
This matters for trans and scalar fpu instructions.

Foz-DB GFX1150:
Totals from 53894 (67.90% of 79377) affected shaders:
Instrs: 38528421 -> 38481337 (-0.12%); split: -0.16%, +0.04%
CodeSize: 200206016 -> 200023916 (-0.09%); split: -0.12%, +0.03%
Latency: 265011734 -> 264303762 (-0.27%); split: -0.28%, +0.02%
InvThroughput: 53804490 -> 53696097 (-0.20%); split: -0.21%, +0.01%
VClause: 736996 -> 736988 (-0.00%); split: -0.00%, +0.00%
SClause: 1118494 -> 1118474 (-0.00%); split: -0.01%, +0.01%
VALU: 21982349 -> 21982358 (+0.00%); split: -0.00%, +0.00%

Foz-DB Navi31:
Totals from 50791 (63.99% of 79377) affected shaders:
Instrs: 37511862 -> 37495712 (-0.04%); split: -0.11%, +0.07%
CodeSize: 197990892 -> 197925104 (-0.03%); split: -0.09%, +0.06%
Latency: 261929261 -> 261273534 (-0.25%); split: -0.27%, +0.01%
InvThroughput: 43978329 -> 43921618 (-0.13%); split: -0.14%, +0.01%
VClause: 727683 -> 727695 (+0.00%); split: -0.00%, +0.00%
SClause: 1092527 -> 1092544 (+0.00%); split: -0.01%, +0.01%
VALU: 22646553 -> 22646566 (+0.00%)

Foz-DB Navi21:
Totals from 43899 (55.30% of 79377) affected shaders:
Instrs: 35649081 -> 35649110 (+0.00%); split: -0.00%, +0.00%
CodeSize: 192336212 -> 192337276 (+0.00%); split: -0.00%, +0.00%
Latency: 270621538 -> 270221431 (-0.15%); split: -0.16%, +0.02%
InvThroughput: 66757841 -> 66715918 (-0.06%); split: -0.07%, +0.01%
VClause: 734884 -> 734867 (-0.00%); split: -0.01%, +0.01%
SClause: 1072956 -> 1072951 (-0.00%); split: -0.01%, +0.01%

Foz-DB Vega10:
Totals from 52687 (83.60% of 63026) affected shaders:
Instrs: 24595280 -> 24595693 (+0.00%); split: -0.01%, +0.01%
CodeSize: 127199836 -> 127200164 (+0.00%); split: -0.01%, +0.01%
Latency: 252281578 -> 252497934 (+0.09%); split: -0.03%, +0.12%
InvThroughput: 136551527 -> 136577609 (+0.02%); split: -0.01%, +0.03%
VClause: 536798 -> 536718 (-0.01%); split: -0.04%, +0.03%
SClause: 819978 -> 819693 (-0.03%); split: -0.04%, +0.01%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
 2025-01-28 17:00:45 +00:00
Georg Lehmann
068f9b51de aco/sched_ilp: use more realistic memory latencies 
The last commit changes order of instructions more aggressively,
and because the memory load latencies here are wastly underestimated,
it ruins some of the work of pre-RA memory scheduling.
With the new heuristic large latency values work fine, so use them.

Foz-DB GFX1150:
Totals from 71343 (89.88% of 79377) affected shaders:
Instrs: 41627671 -> 41915029 (+0.69%); split: -0.01%, +0.70%
CodeSize: 215901308 -> 217051132 (+0.53%); split: -0.01%, +0.54%
Latency: 288714439 -> 286556159 (-0.75%); split: -0.76%, +0.02%
InvThroughput: 55834139 -> 55645301 (-0.34%); split: -0.35%, +0.01%
VClause: 829066 -> 828984 (-0.01%); split: -0.04%, +0.03%
SClause: 1237366 -> 1237448 (+0.01%); split: -0.02%, +0.02%
VALU: 23643291 -> 23643292 (+0.00%); split: -0.00%, +0.00%

Foz-DB Navi31:
Totals from 70576 (88.91% of 79377) affected shaders:
Instrs: 40928125 -> 41211820 (+0.69%); split: -0.01%, +0.70%
CodeSize: 215770956 -> 216897948 (+0.52%); split: -0.00%, +0.53%
Latency: 288139802 -> 286038405 (-0.73%); split: -0.75%, +0.02%
InvThroughput: 46391629 -> 46300275 (-0.20%); split: -0.20%, +0.01%
VClause: 829987 -> 829997 (+0.00%); split: -0.02%, +0.02%
SClause: 1229345 -> 1229425 (+0.01%); split: -0.02%, +0.02%
VALU: 24515334 -> 24515335 (+0.00%)

Foz-DB Navi21:
Instrs: 45512672 -> 45527322 (+0.03%); split: -0.01%, +0.04%
CodeSize: 244254716 -> 244311472 (+0.02%); split: -0.01%, +0.03%
Latency: 314034443 -> 311473726 (-0.82%); split: -0.83%, +0.01%
InvThroughput: 73373201 -> 73220438 (-0.21%); split: -0.21%, +0.00%
VClause: 914819 -> 914853 (+0.00%); split: -0.02%, +0.02%
SClause: 1283331 -> 1283302 (-0.00%); split: -0.01%, +0.01%

Foz-DB Vega10:
Totals from 41908 (66.49% of 63026) affected shaders:
Instrs: 22770415 -> 22779136 (+0.04%); split: -0.01%, +0.04%
CodeSize: 118195752 -> 118230540 (+0.03%); split: -0.00%, +0.03%
Latency: 242119940 -> 239665380 (-1.01%); split: -1.02%, +0.01%
InvThroughput: 131459884 -> 131182979 (-0.21%); split: -0.21%, +0.00%
VClause: 493311 -> 493215 (-0.02%); split: -0.05%, +0.03%
SClause: 758814 -> 758761 (-0.01%); split: -0.02%, +0.01%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
 2025-01-28 17:00:45 +00:00
Georg Lehmann
ce897b336e aco/sched_ilp: rename priority to wait_cycles 
And invert.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
 2025-01-28 17:00:44 +00:00
Georg Lehmann
819938d2fa aco/sched_ilp: new latency heuristic 
The main train of thought is that we should consider latency after
the write was scheduled. This means we rely a lot less on the input
order of instructions for good results.

Foz-DB GFX1150:
Totals from 75606 (95.25% of 79377) affected shaders:
Instrs: 43274326 -> 42129011 (-2.65%); split: -2.65%, +0.01%
CodeSize: 223049932 -> 218465796 (-2.06%); split: -2.06%, +0.00%
Latency: 297614199 -> 292317054 (-1.78%); split: -1.84%, +0.06%
InvThroughput: 57020160 -> 56336213 (-1.20%); split: -1.21%, +0.02%
VClause: 841775 -> 841861 (+0.01%); split: -0.06%, +0.07%
SClause: 1253516 -> 1253798 (+0.02%); split: -0.03%, +0.05%
VALU: 23893837 -> 23893828 (-0.00%); split: -0.00%, +0.00%

Foz-DB Navi31:
Totals from 75606 (95.25% of 79377) affected shaders:
Instrs: 42717592 -> 41531696 (-2.78%); split: -2.78%, +0.00%
CodeSize: 223582476 -> 218866196 (-2.11%); split: -2.11%, +0.00%
Latency: 297736383 -> 292450493 (-1.78%); split: -1.83%, +0.05%
InvThroughput: 47298730 -> 46934084 (-0.77%); split: -0.78%, +0.01%
VClause: 844982 -> 844892 (-0.01%); split: -0.07%, +0.06%
SClause: 1248433 -> 1248693 (+0.02%); split: -0.03%, +0.05%
VALU: 24819703 -> 24819704 (+0.00%); split: -0.00%, +0.00%

Foz-DB Navi21:
Totals from 76224 (96.03% of 79377) affected shaders:
Instrs: 46019515 -> 46015691 (-0.01%); split: -0.03%, +0.03%
CodeSize: 246992544 -> 246977404 (-0.01%); split: -0.03%, +0.02%
Latency: 324647457 -> 318661132 (-1.84%); split: -1.90%, +0.05%
InvThroughput: 74834800 -> 74269723 (-0.76%); split: -0.76%, +0.01%
VClause: 927601 -> 927579 (-0.00%); split: -0.04%, +0.04%
SClause: 1302666 -> 1303178 (+0.04%); split: -0.02%, +0.06%

Foz-DB Vega10:
Totals from 60142 (95.42% of 63026) affected shaders:
Instrs: 25117688 -> 25098175 (-0.08%); split: -0.10%, +0.02%
CodeSize: 129847464 -> 129769456 (-0.06%); split: -0.08%, +0.02%
Latency: 261606546 -> 262407481 (+0.31%); split: -0.12%, +0.43%
InvThroughput: 138422594 -> 138500401 (+0.06%); split: -0.03%, +0.09%
VClause: 555424 -> 555321 (-0.02%); split: -0.11%, +0.09%
SClause: 851219 -> 851620 (+0.05%); split: -0.03%, +0.08%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
 2025-01-28 17:00:44 +00:00
Eric Engestrom
dd2629b8b8 radv,lvp: fix url to VkAabbPositionsKHR docs 
The current URL redirect to a page that does not contain any information
about this struct, so let's fix that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33159>
 2025-01-28 14:28:59 +00:00
Samuel Pitoiset
50a0d1fd65 radv: disable VK_KHR_cooperative_matrix on GFX12 
I have it mostly but it won't be ready in time for 25.0 and the changes
are probably too large for a backport.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33257>
 2025-01-28 13:27:55 +00:00
Samuel Pitoiset
9d528b9966 radv: disable video support on GFX12 
VCN 5.0+ isn't yet implemented.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33253>
 2025-01-28 12:09:43 +00:00
Samuel Pitoiset
c172f6ef01 radv: fix disabling logic op for srgb/float formats when blending is enabled 
The Vulkan spec says:
    "If logicOpEnable is VK_TRUE, then a logical operation selected by
     logicOp is applied between each color attachment and the
     fragment’s corresponding output value, and blending of all
     attachments is treated as if it were disabled. Any attachments
     using color formats for which logical operations are not supported
     simply pass through the color values unmodified."

When logic op and blending are both enabled, logic op takes precedence
and values should be passed through unmodified. Also RB+ shouldn't
have any effects when blending is disabled.

Fixes new VKCTS coverage dEQP-VK.pipeline.*.logic_op_na_formats.*.

Fixes: 03b037a0e3 ("radv: disable logic op for float/srgb formats")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33235>
 2025-01-28 08:19:15 +00:00
Samuel Pitoiset
d857198c87 radv/ci: update descriptor buffer skipped tests 
More subsets have been added (eg. sparse).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33237>
 2025-01-28 07:49:54 +00:00
Mike Blumenkrantz
4e1b18178b aco: exclude novalidateir from codegen flags 
this otherwise bricks caching

cc: mesa-stable

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33239>
 2025-01-27 19:15:47 +00:00
Samuel Pitoiset
0f5bd032eb ci: update VKCTS main to a9988483c0864d7190e5e6264ccead95423dfd00 
RADV is the only driver using VKCTS main.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <None>
Reviewed-by: Eric Engestrom <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33186>
 2025-01-27 13:50:01 +00:00
Georg Lehmann
df1de388a3 aco/sched_ilp: reorder VINTRP 
VINTRP(gfx6-gfx10.3) is mostly just VALU, but we treated it like memory
instructions as an afterthought. This had issues as VINTRP was never reordered
with itself, or other memory instructions. Reordering VINTRP in clauses
increases ILP. We don't really need collect_clause_dependencies for VINTRP
either, because they ususally have the same dependencies already. That means
we can still form VINTRP clauses by selecting preferably VINTRP after a
previous one.

Foz-DB Navi21:
Totals from 34184 (43.16% of 79206) affected shaders:
Instrs: 18811270 -> 18812046 (+0.00%); split: -0.01%, +0.02%
CodeSize: 103627276 -> 103630056 (+0.00%); split: -0.01%, +0.01%
Latency: 188379364 -> 187936731 (-0.23%); split: -0.27%, +0.03%
InvThroughput: 42600163 -> 42590608 (-0.02%); split: -0.03%, +0.00%
VClause: 378960 -> 378912 (-0.01%); split: -0.02%, +0.00%
SClause: 727560 -> 720573 (-0.96%); split: -1.08%, +0.12%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Daniel Schürmann <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33111>
 2025-01-27 11:59:45 +00:00
Georg Lehmann
45ccd6487f aco/sched_ilp: only remove WaW/WaR for inter clause dependencies 
Direct RaW shouldn't be removed, because the clause is split by a wait anyway.

Foz-DB Navi21:
Totals from 52 (0.07% of 79206) affected shaders:
Instrs: 1603523 -> 1603485 (-0.00%); split: -0.00%, +0.00%
CodeSize: 8223048 -> 8222788 (-0.00%)
Latency: 9741674 -> 9738884 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 2322621 -> 2322010 (-0.03%); split: -0.03%, +0.00%
SClause: 31325 -> 31320 (-0.02%); split: -0.02%, +0.01%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Daniel Schürmann <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33111>
 2025-01-27 11:59:45 +00:00
Georg Lehmann
4b332afb32 aco/sched_ilp: add dependencies of later clause instrs more aggressively 
Foz-DB GFX1150:
Totals from 22246 (28.03% of 79377) affected shaders:
Instrs: 22689053 -> 22684012 (-0.02%); split: -0.06%, +0.03%
CodeSize: 117622416 -> 117603292 (-0.02%); split: -0.04%, +0.03%
Latency: 182725630 -> 182702465 (-0.01%); split: -0.06%, +0.05%
InvThroughput: 37963256 -> 37956961 (-0.02%); split: -0.03%, +0.02%
VClause: 471019 -> 467248 (-0.80%)
SClause: 592620 -> 590034 (-0.44%); split: -0.44%, +0.01%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Daniel Schürmann <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33111>
 2025-01-27 11:59:45 +00:00