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aco: Move NGG pos export scheduling determination to drivers.

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And don't schedule them on GFX11+ at all.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33218>
This commit is contained in:
Timur Kristóf 2025-01-25 12:12:36 +01:00 • committed by Marge Bot
parent 7a3d95bbe2
commit e9069eec8a
4 changed files with 8 additions and 11 deletions
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8
src/amd/compiler/aco_scheduler.cpp
View file

@ -1271,11 +1271,9 @@ schedule_program(Program* program)
* Schedule less aggressively when early primitive export is used, and
* keep the position export at the very bottom when late primitive export is used.
*/
if (program->info.has_ngg_culling && program->stage.num_sw_stages() == 1) {
if (!program->info.has_ngg_early_prim_export)
ctx.schedule_pos_exports = false;
else
ctx.schedule_pos_export_div = 4;
if (program->info.hw_stage == AC_HW_NEXT_GEN_GEOMETRY_SHADER) {
ctx.schedule_pos_exports = program->info.schedule_ngg_pos_exports;
ctx.schedule_pos_export_div = 4;
}
for (Block& block : program->blocks)

3
src/amd/compiler/aco_shader_info.h
View file

@ -108,8 +108,7 @@ struct aco_ps_prolog_info {
struct aco_shader_info {
enum ac_hw_stage hw_stage;
uint8_t wave_size;
bool has_ngg_culling;
bool has_ngg_early_prim_export;
bool schedule_ngg_pos_exports; /* Whether we should schedule position exports up or not. */
bool image_2d_view_of_3d;
unsigned workgroup_size;
bool merged_shader_compiled_separately; /* GFX9+ */

3
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -28,8 +28,6 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
const enum amd_gfx_level gfx_level)
{
ASSIGN_FIELD(wave_size);
ASSIGN_FIELD(has_ngg_culling);
ASSIGN_FIELD(has_ngg_early_prim_export);
ASSIGN_FIELD(workgroup_size);
ASSIGN_FIELD(ps.has_epilog);
ASSIGN_FIELD(merged_shader_compiled_separately);
@ -48,6 +46,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
aco_info->hw_stage = radv_select_hw_stage(radv, gfx_level);
aco_info->tcs.tcs_offchip_layout = radv_args->tcs_offchip_layout;
aco_info->next_stage_pc = radv_args->next_stage_pc;
aco_info->schedule_ngg_pos_exports = gfx_level < GFX11 && radv->has_ngg_culling && radv->has_ngg_early_prim_export;
}
static inline void

5
src/gallium/drivers/radeonsi/si_shader_aco.c
View file

@ -76,8 +76,9 @@ si_fill_aco_shader_info(struct si_shader *shader, struct aco_shader_info *info,
info->hw_stage = si_select_hw_stage(stage, key, gfx_level);
if (stage <= MESA_SHADER_GEOMETRY && key->ge.as_ngg && !key->ge.as_es) {
info->has_ngg_culling = si_shader_culling_enabled(shader);
info->has_ngg_early_prim_export = gfx10_ngg_export_prim_early(shader);
info->schedule_ngg_pos_exports = sel->screen->info.gfx_level < GFX11 &&
si_shader_culling_enabled(shader) &&
gfx10_ngg_export_prim_early(shader);
}
switch (stage) {