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ac,radeonsi: add SDMA DCC tiling for GFX12+

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33284>
This commit is contained in:
Samuel Pitoiset 2025-01-29 05:33:38 -08:00 • committed by Marge Bot
parent e639cd768d
commit fe6494559d
2 changed files with 14 additions and 6 deletions
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8
src/amd/common/sid.h
View file

@ -389,6 +389,14 @@
#define SDMA_NOP_PAD SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) /* header-only version */
/* SDMA DCC tilings for GFX12+ */
#define SDMA_DCC_DATA_FORMAT(x) ((x) & 0x3f)
#define SDMA_DCC_NUM_TYPE(x) (((x) & 0x7) << 9)
#define SDMA_DCC_READ_CM(x) (((x) & 0x3) << 16) /* 0: bypass DCC, 2: decompress reads if PTE.D */
#define SDMA_DCC_WRITE_CM(x) (((x) & 0x3) << 18) /* 0: bypass DCC, 1: write compressed if PTE.D, 2: write uncompressed if PTE.D */
#define SDMA_DCC_MAX_COM(x) (((x) & 0x3) << 24)
#define SDMA_DCC_MAX_UCOM(x) (((x) & 0x1) << 26) /* 1: max uncompressed block size 256B */
enum amd_cmp_class_flags
{
S_NAN = 1 << 0, // Signaling NaN

12
src/gallium/drivers/radeonsi/si_sdma_copy_image.c
View file

@ -171,12 +171,12 @@ static bool si_sdma_v4_v5_copy_texture(struct si_context *sctx, struct si_textur
uint64_t md_address = tiled_address + tiled->surface.meta_offset;
if (is_v7) {
radeon_emit(data_format |
number_type << 9 |
(2 << 16) | /* 0: bypass DCC, 2: decompress reads if PTE.D */
(1 << 18) | /* 0: bypass DCC, 1: write compressed if PTE.D, 2: write uncompressed if PTE.D */
(tiled->surface.u.gfx9.color.dcc.max_compressed_block_size << 24) |
(1 << 26)); /* max uncompressed block size: 256B */
radeon_emit(SDMA_DCC_DATA_FORMAT(data_format) |
SDMA_DCC_NUM_TYPE(number_type) |
SDMA_DCC_READ_CM(2) |
SDMA_DCC_WRITE_CM(1) |
SDMA_DCC_MAX_COM(tiled->surface.u.gfx9.color.dcc.max_compressed_block_size) |
SDMA_DCC_MAX_UCOM(1));
} else {
/* Add metadata */
radeon_emit((uint32_t)md_address);