Commit graph

114745 commits

Author SHA1 Message Date
Samuel Pitoiset
637a9cbd3b radv: force enable VK_AMD_shader_ballot for Wolfenstein Youngblood
This gives a nice boost, +20% at this time on my Vega 56. Shader
ballot should be enabled by default at some point but it reduces
performance a bit (-6%) with Wolfeinstein II. Enable it only for
Youngblood at the moment, like what we did for Talos in the past.

As a bonus point, it gets rid of some minor artifacts that only
happens when ballot is disabled for some reasons.

Cc: 19.2 <mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit a6ad9e8ccf)
2019-09-04 11:51:15 -07:00
Samuel Pitoiset
690f050608 radv: add a new debug option called RADV_DEBUG=noshaderballot
Shader ballot will be enabled by default for Wolfenstein
Youngblood. This follows what we did for sisched.

Cc: 19.2 <mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit f202ac27a9)
2019-09-04 11:50:59 -07:00
Samuel Pitoiset
3ab1368c4f radv: allow to enable VK_AMD_shader_ballot only on GFX8+
Scans aren't implemented on SI/CIK.

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit e73d863a66)
2019-09-04 11:50:53 -07:00
Danylo Piliaiev
71daf2ef67 nir/loop_unroll: Prepare loop for unrolling in wrapper_unroll
Without loop_prepare_for_unroll loops are losing phis.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111411
Fixes: 5db98195 "nir: add loop unroll support for wrapper loops"
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 84b3ef6a96)
2019-09-04 11:50:48 -07:00
Bas Nieuwenhuizen
614def1a89 radv: Emit VGT_GS_ONCHIP_CNTL for tess on GFX10.
Otherwise hangs are possible. This register was already set for
GS and NGG.

Fixes: 5eaed7ecfc "radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit e04761d0f9)
2019-09-04 11:50:42 -07:00
Bas Nieuwenhuizen
55334521f7 radv: Use correct vgpr_comp_cnt for VS if both prim_id and instance_id are needed.
Should take the max of the 2.

Fixes: ea337c8b7e "radv/gfx10: fix VS input VGPRs with the legacy path"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 2e763f7c87)
2019-09-04 11:50:37 -07:00
Ilia Mirkin
8ee40f6b63 gallium/vl: use compute preference for all multimedia, not just blit
The compute paths in vl are a bit AMD-specific. For example, they (on
nouveau), try to use a BGRX8 image format, which is not supported.
Fixing all this is probably possible, but since the compute paths aren't
in any way better, it's difficult to care.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213
Fixes: 9364d66cb7 (gallium/auxiliary/vl: Add video compositor compute shader render)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 958390a9bf)
2019-09-04 11:50:32 -07:00
Marek Olšák
25de459644 radeonsi: consolidate determining VGPR_COMP_CNT for API VS 2019-08-27 16:10:40 -04:00
Marek Olšák
5d7754017c radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags
We need two different values of the register, one for NGG and one for
legacy, in order to fix edge flags for the legacy pipeline.

Passing the ngg flag to emit_clip_regs would be too complicated,
so CONTEXT_REG_RMW is used for partial register updates.
2019-08-27 16:10:40 -04:00
Marek Olšák
d23bf14d44 radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables
It varies depending on si_shader_key::as_ngg.
2019-08-27 16:10:40 -04:00
Marek Olšák
514eb1587e radeonsi: add PKT3_CONTEXT_REG_RMW 2019-08-27 16:10:40 -04:00
Marek Olšák
a935da7cef winsys/amdgpu+radeon: process AMD_DEBUG in addition to R600_DEBUG 2019-08-27 16:10:40 -04:00
Marek Olšák
b9330a6189 radeonsi/gfx10: add AMD_DEBUG=nongg 2019-08-27 16:10:40 -04:00
Marek Olšák
0207c318e0 radeonsi/gfx10: finish up Navi14, add PCI ID 2019-08-27 16:10:40 -04:00
Marek Olšák
e09d469622 radeonsi/gfx10: always use the legacy pipeline for streamout
The best way to prevent GDS hangs is not to use GDS.
2019-08-27 16:10:40 -04:00
Marek Olšák
f208b04dba radeonsi/gfx10: don't initialize VGT_INSTANCE_STEP_RATE_0
Only gfx9 and older use it to get InstanceID in VGPR1.
2019-08-27 16:10:40 -04:00
Marek Olšák
c0716446a4 radeonsi/gfx10: fix InstanceID for legacy VS+GS 2019-08-27 16:10:40 -04:00
Marek Olšák
4d3097f36a radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
Legacy GS only works with Wave64.
2019-08-27 16:10:40 -04:00
Marek Olšák
a3a266807e radeonsi/gfx10: create the GS copy shader if using legacy streamout 2019-08-27 16:10:40 -04:00
Marek Olšák
beea2dee8a radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy streamout 2019-08-27 16:10:40 -04:00
Marek Olšák
78c603ebf5 radeonsi/gfx10: fix tessellation for the legacy pipeline
ported from PAL
2019-08-27 16:10:40 -04:00
Marek Olšák
3dec21a8aa radeonsi: move some global shader cache flags to per-binary flags 2019-08-27 16:10:40 -04:00
Marek Olšák
6e07ac3343 radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache
It could load an NGG shader when we want a legacy shader and vice versa.
2019-08-27 16:10:40 -04:00
Emil Velikov
c0b9399d9d Update version to 19.2.0-rc1
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-20 23:18:37 +01:00
Erico Nunes
71fb721ca5 lima/ppir: use ra_get_best_spill_node to select spill node
ra_get_best_spill_node is what other users of the mesa register
allocator use.
Switching to it now also fixes an infinite loop issue with ppir regalloc
with the ppir control flow patchset, and also provides a small gain over
the previous herusitic on number of spilled nodes testing with
shader-db.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-08-20 21:16:02 +00:00
Eric Anholt
c1dc84e71d tgsi: Remove unused tgsi_check_soa_dependencies().
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2019-08-20 13:31:13 -07:00
Eric Anholt
4ebe6b2e72 tgsi: Drop the SSE2 constants setup that's been dead code since 2011.
The SSE2 executor was removed in 4eb3225b38 ("Remove tgsi_sse2.")

Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2019-08-20 13:31:13 -07:00
Eric Anholt
98c58355d3 tgsi: drop a stale comment
This was fixed in 912ed84f83 ("tgsi: move to using vector for system
values.")

Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2019-08-20 13:31:13 -07:00
Eric Anholt
553cd82d64 gitlab-ci: Enable the GLES2/3 CTS on softpipe.
The GLES2 CTS takes about 8 minutes of total runtime (at parallel 4 is
~2 minutes in the test stage if runners are free), while GLES3 takes
about 25.  Since the GLES3 run is pretty expensive, just do a cheap
touch test of 1 out of every 10 tests in the test list on MRs, until
we can get the runtime down.

v2: Drop the full run for now until we can bring runtime down or bring
    up a dedicated mesa runner.

Reviewed-by: Eric Engestrom <eric@engestrom.ch> (v1)
Reviewed-By: Gert Wollny <gert.wollny@collabora.com> (v1)
2019-08-20 13:31:13 -07:00
Jose Maria Casanova Crespo
6c904773fe mesa: reverse no_error on compressed_tex_sub_image for TEX_MODE_CURRENT
This fixes the regression introduced on "mesa: refactor
compressed_tex_sub_image function" that started to crash
KHR-GLES2.texture_3d.compressed_texture.negative_compressed_tex_sub_image

Fixes: 7df233d68d ("mesa: refactor compressed_tex_sub_image function")
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-20 20:45:21 +01:00
Adam Jackson
b283919398 glx: Eliminate glx_config::{rgb,float,colorIndex}Mode
These are redundant with glx_config::renderType, let's just use that
consistently.
2019-08-20 14:05:07 -04:00
Adam Jackson
74ca87e4bc glx: Remove unused glx_config::pixmapMode
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:05:03 -04:00
Adam Jackson
35fc7bdf0e glx: convert glx_config_create_list to one big calloc
Simpler, less failure prone, less malloc overhead, what's not to like.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:05:01 -04:00
Adam Jackson
97d58eabcc glx: convert a malloc+memset to calloc
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:04:59 -04:00
Adam Jackson
cabd09c9e7 glx: Fix parameter documentation of glx_config_create_list
'minimum_size' is not, in fact, an argument to this function.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:04:56 -04:00
Arcady Goldmints-Orlov
3835535537 anv: inline uniforms blocks don't count toward descriptor set limits
In a descriptor set inline uniform blocks don't use up any bindings.
However, the presence of any inline uniform blocks doed require the
use of the descriptor buffer, which takes up one binding.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 16:48:45 +00:00
Daniel Schürmann
df86c5ffb3 nir: add divergence analysis pass.
This pass expects the shader to be in LCSSA form.
The algorithm is based on 'The Simple Divergence Analysis' from
Diogo Sampaio, Rafael De Souza, Sylvain Collange, Fernando Magno Quintão Pereira.
Divergence Analysis. ACM Transactions on Programming Languages and Systems (TOPLAS)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-08-20 17:40:13 +02:00
Rhys Perry
7b07034931 nir/subgroups: Lower clustered reductions with cluster_size >= subgroup_size into reductions
The behavior for reductions with cluster_size >= subgroup_size is implementation defined.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:40:10 +02:00
Rhys Perry
911a1dfad2 nir/lcssa: allow to create LCSSA phis for loop-invariant booleans
ACO depends on LCSSA phis for divergent booleans to work correctly.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:40:05 +02:00
Daniel Schürmann
9c40ad49d5 nir/lcssa: Skip loop invariant variables when converting to LCSSA.
Co-authored-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:40:01 +02:00
Rhys Perry
8a6cfaa15a nir: make nir_to_lcssa() a general NIR pass.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:39:54 +02:00
Daniel Schürmann
204846ad06 nir/lcssa: handle deref instructions properly
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 414148cdc1 "nir: Support deref instructions in loop_analyze"
2019-08-20 17:39:52 +02:00
Jose Maria Casanova Crespo
7c56a68c8b tgsi_to_nir: only update TGSI properties of the current shader stage
The implementation introduced in "tgsi_to_nir: be careful about not
losing any TGSI properties silently (v2)" updates all the TGSI properties,
but it didn't take into account that the shader_info structure uses a union
to store the different attributes for each shader stage.

Now we only update the attributes if they affect current shader stage,
avoiding to overwrite members of the union that should be overwritten.
This has created hundreds of regressions in v3d.

For example the TGSI_PROPERTY_VS_BLIT_SGPRS_AMD was overwritting the
same position used by TGSI_PROPERY_CS_FIXED_BLOCK_DEPTH.

Fixes: e300365197 ("tgsi_to_nir: be careful about not losing any TGSI properties silently (v2)")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-20 10:30:21 +00:00
Samuel Pitoiset
83a63a5b12 radv/gfx10: do not emit PA_SC_TILE_STEERING_OVERRIDE twice
CLEAR_STATE emits it for us.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-08-20 12:13:44 +02:00
Samuel Pitoiset
2ca8629fa9 radv: do not emit PKT3_CONTEXT_CONTROL with AMDGPU 3.6.0+
It's emitted by the kernel.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-08-20 12:13:41 +02:00
Gert Wollny
6a09405368 mesa/program: Take ARB_framebuffers_no_attachments into account in wpos correction
If a drawbuffer is an fbo without an attachment then its 'Height' will be zero,
and we have to take its 'DefaultGeometry.Height' into account.

Fixes on softpipe (with the exception of tests that use multisample):
  dEQP-GLES31.functional.fbo.no_attachments.*

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-20 10:04:24 +02:00
Sagar Ghuge
fe0e9db797 iris: Enable non coherent framebuffer fetch on broadwell
v2: Use GEN_GEN in iris_state (Kenneth Graunke)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:58 -07:00
Sagar Ghuge
57ce422e20 iris: Free resource if failed to allocate surface state
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:55 -07:00
Sagar Ghuge
02244bc515 iris: Pass isl_surf to fill_surface_state
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:45 -07:00
Sagar Ghuge
638a157e02 iris: Add infrastructure to support non coherent framebuffer fetch
Create separate SURFACE_STATE for render target read in order to support
non coherent framebuffer fetch on broadwell.

Also we need to resolve framebuffer in order to support CCS_D.

v2: Add outputs_read check (Kenneth Graunke)

v3: 1) Import Curro's comment from get_isl_surf
    2) Rename get_isl_surf method
    3) Clean up allocation in case of failure

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:44 -07:00