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213674 commits

Author SHA1 Message Date
Dylan Baker
d9812eaea8 VERSION: bump for rc2
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Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2025-10-22 16:13:33 -07:00
Benjamin Cheng
be191ceff7 radv/video_enc: Cleanup slice count assert
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This was left over when first enabling multiple slice encoding.

Fixes: 63e952ff2c ("radv/video: Support encoding multiple slices")
Reviewed-by: David Rosca <david.rosca@amd.com>
(cherry picked from commit b6d6c1af73)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:39 -07:00
Pierre-Eric Pelloux-Prayer
49bfddbd11 radeonsi: propagate shader updates for merged shaders
In case of merged shaders (eg: VS+GS), a change to VS should trigger
a GS update.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13935
Fixes: b1a34ac95d ("radeonsi: change do_update_shaders boolean to a bitmask")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 90103fe618)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:39 -07:00
Faith Ekstrand
0182cde848 util: Build util/cache_ops_x86.c with -msse2
__builtin_ia32_clflush() requires -msse2 so we need to set -msse2 at
least for building that file.  Fortunately, there are no GPUs that
actually need userspace cache flushing that can ever be bolted onto a
pre-SSE2 x86 CPUs.

Fixes: 555881e574 ("util/cache_ops: Add some cache flush helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14134
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
(cherry picked from commit efbecd93ba)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:38 -07:00
Faith Ekstrand
94ec7c686d util: Don't advertise cache ops on x86 without SSE2
Fixes: 555881e574 ("util/cache_ops: Add some cache flush helpers")
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
(cherry picked from commit 3739d7a90c)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:37 -07:00
Olivia Lee
4202ea6c7f panfrost: fix cl_local_size for precompiled shaders
nir_lower_compute_system_values will attempt to lower
load_workgroup_size unless workgroup_size_variable is set. For precomp
shaders, the workgroup size is set statically for each entrypoint by
nir_precompiled_build_variant. Because we call
lower_compute_system_values early, it sets the workgroup size to zero.
Temporarily setting workgroup_size_variable while we are still
processing all the entrypoints together inhibits this.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: 20970bcd96 ("panfrost: Add base of OpenCL C infrastructure")
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit a410d90fd2)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:37 -07:00
Rhys Perry
10475e8ac1 amd/lower_mem_access_bit_sizes: fix shared access when bytes<bit_size/8
This can happen with (for example) 32x2 loads with
align_mul=4,align_offset=2.

This patch does bit_size=min(bit_size,bytes) to prevent num_components
from being 0.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 52cd5f7e69 ("ac/nir_lower_mem_access_bit_sizes: Split unsupported shared memory instructions")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit b18421ae3d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:36 -07:00
Rhys Perry
c1cf6e75ae amd/lower_mem_access_bit_sizes: be more careful with 8/16-bit scratch load
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.3
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit e89b22280f)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:34 -07:00
Rhys Perry
2b8675fd86 amd/lower_mem_access_bit_sizes: improve subdword/unaligned SMEM lowering
Summary of changes:
- handle unaligned 16-bit scalar loads when supported_dword=true
- increases the size of 8/16/32/64-bit buffer loads which are not dword
  aligned, which can create less SMEM loads.
- handles when "bytes" is less than "bit_size / 8"

fossil-db (gfx1201):
Totals from 26 (0.03% of 79839) affected shaders:
Instrs: 12676 -> 12710 (+0.27%); split: -0.30%, +0.57%
CodeSize: 67272 -> 67384 (+0.17%); split: -0.24%, +0.40%
Latency: 44399 -> 44375 (-0.05%); split: -0.09%, +0.04%
SClause: 352 -> 344 (-2.27%)
SALU: 3972 -> 3992 (+0.50%)
SMEM: 554 -> 528 (-4.69%)

fossil-db (navi21):
Totals from 6 (0.01% of 79825) affected shaders:
Instrs: 2192 -> 2186 (-0.27%)
CodeSize: 12188 -> 12140 (-0.39%)
Latency: 10037 -> 10033 (-0.04%); split: -0.12%, +0.08%
SMEM: 124 -> 118 (-4.84%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: fbf0399517 ("amd/lower_mem_access_bit_sizes: lower all SMEM instructions to supported sizes")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit 8829fc3bd6)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:32 -07:00
Rhys Perry
e967da84a8 amd/lower_mem_access_bit_sizes: don't create subdword UBO loads with LLVM
These are unsupported.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14127
Fixes: fbf0399517 ("amd/lower_mem_access_bit_sizes: lower all SMEM instructions to supported sizes")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit 79b2fa785d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:31 -07:00
Dylan Baker
2a8f2ff397 .pick_status.json: Update to e38491eb18
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-22 09:03:27 -07:00
Mel Henning
7a30a71c45 nvk: VK_DEPENDENCY_ASYMMETRIC_EVENT_BIT_KHR
This was missed in the original maintenance9 MR.

Fixes the flakes in test
dEQP-VK.synchronization2.op.single_queue.event.write_ssbo_compute_read_ssbo_compute.buffer_16384_maintenance9

Fixes: 7692d3c0 ("nvk: Advertise VK_KHR_maintenance9")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
(cherry picked from commit 28fbc6addb)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:55 -07:00
Karol Herbst
9c57c0a194 nak: fix MMA latencies on Ampere
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Fixes: 7a01953a39 ("nak: Add Ampere and Ada latency information")
(cherry picked from commit e7dca5a6ca)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:54 -07:00
Karol Herbst
425c49ebf2 nak: ensure deref has a ptr_stride in cmat load/store lowering
With untyped pointer we might get a deref_cast with a 0 ptr_stride. But we
were supposed to ignore the stride information on the pointer anyway, so
let's do that properly now.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Fixes: 05dca16143 ("nak: extract nir_intrinsic_cmat_load lowering into a function")
(cherry picked from commit 3bbf3f7826)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:54 -07:00
Karol Herbst
7b7cb63a14 nak: extract cmat load/store element offset calculation
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Fixes: 05dca16143 ("nak: extract nir_intrinsic_cmat_load lowering into a function")
(cherry picked from commit f632bfc715)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:53 -07:00
Faith Ekstrand
1941ada4a6 panvk: Fix integer dot product properties
We already set has_[su]dot_4x8[_sat] in nir_shader_compiler_options so
we're already getting the opcodes.  We just need to advertise the
features properly.  If bifrost_compile.h is to be believed, those are
all available starting at gen 9.

Closes: https://gitlab.freedesktop.org/panfrost/mesa/-/issues/218
Closes: https://gitlab.freedesktop.org/panfrost/mesa/-/issues/219
Fixes: f7f9b3d170 ("panvk: Move to vk_properties")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
(cherry picked from commit 38950083ae)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:52 -07:00
Lionel Landwerlin
e982234bb6 nir/divergence: fix handling of intel uniform block load
Those are normally uniform always, but for the purpose of fused
threads handling, we need to check their sources.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ca1533cd03 ("nir/divergence: add a new mode to cover fused threads on Intel HW")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 255d1e883d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:52 -07:00
Lionel Landwerlin
dbbadebe13 brw: fix ballot() type operations in shaders with HALT instructions
Fixes dEQP-VK.reconvergence.terminate_invocation.bit_count

LNL fossildb stats:

 Totals from 16489 (3.36% of 490184) affected shaders:
 Instrs: 3710499 -> 3710500 (+0.00%)
 Cycle count: 91601018 -> 90305642 (-1.41%); split: -1.81%, +0.40%
 Max dispatch width: 523936 -> 523952 (+0.00%); split: +0.02%, -0.01%

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 757c042e39)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:51 -07:00
Lionel Landwerlin
0d100cc078 brw: only consider cross lane access on non scalar VGRFs
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1bff4f93ca ("brw: Basic infrastructure to store convergent values as scalars")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit 70aa028f27)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:50 -07:00
Lionel Landwerlin
f656d062e3 brw: constant fold u2u16 conversion on MCS messages
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: bddfbe7fb1 ("brw/blorp: lower MCS fetching in NIR")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit f48c9c3a37)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:50 -07:00
Mel Henning
847ad886d6 nvk: Really fix maxVariableDescriptorCount w/ iub
I didn't test "nvk: Fix maxVariableDescriptorCount with iub" as
thoroughly as I should have and it regressed
dEQP-VK.api.maintenance3_check.descriptor_set because we were then
violating the requirement that maxPerSetDescriptors describes a limit
that's guaranteed to be supported (and reported as supported in
GetDescriptorSetLayoutSupport).

That commit was also based on a misreading of nvk_nir_lower_descriptors.c
where I thought that the end offset of an inline uniform block needed to
be less than the size of a UBO. That is not the case - on closer
inspection that code gracefully falls back to placing IUBs in globablmem
if necessary. So, we can afford to be less strict about our IUB sizing
and only require that IUBs follow the existing limit imposed by
maxInlineUniformBlockSize.

Fixes: ff7f785f09 ("nvk: Fix maxVariableDescriptorCount with iub")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
(cherry picked from commit 77cd629b34)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:48 -07:00
Emma Anholt
5dcc65643c nir/shrink_stores: Don't shrink stores to an invalid num_components.
Avoids a regression in the CL CTS on the next commit.

Fixes: 2dba7e6056 ("nir: split nir_opt_shrink_stores from nir_opt_shrink_vectors")
(cherry picked from commit 537cc4e0ff)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:47 -07:00
Yiwei Zhang
ab7bda0a1b panvk: fix to advance vs res_table properly
Fix a regression from an unfortunate typo.

Fixes: 48e8d6d207 ("panfrost, panvk: The size of resource tables needs to be a multiple of 4.")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
(cherry picked from commit 387f75f43d)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:29 -07:00
Yiwei Zhang
a02d8d5767 panvk: fix to advance vs driver_set properly
Should only set once outside the multidraw loop so that per draw can
patch its own own desc attribs when needed.

Fixes: a5a0dd3ccc ("panvk: Implement multiDrawIndirect for v10+")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
(cherry picked from commit 800c4d3430)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:29 -07:00
Timur Kristóf
13fa1460dd ac/nir/ngg_mesh: Lower num_subgroups to constant
Mesh shader workgroups always have the same amount of subgroups.

When the API workgroup size is the same as the real workgroup
size, this is a small optimization (using a constant instead of
a shader arg).

When the API workgroup size is smaller than the real workgroup
size (eg. when the number of output vertices or primitves is
greater than the API workgroup size on RDNA 2), this fixes a
potential bug because num_subgroups would return the "real"
workgroup size instead of the API one.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
(cherry picked from commit d20049b430)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:29 -07:00
Patrick Lerda
14544ef278 r600: update nplanes support
This change fixes "piglit/bin/ext_image_dma_buf_import-export -auto".

Fixes: 02aaf360ae ("r600: Implement resource_get_param")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 84dc9af3d4)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:28 -07:00
Patrick Lerda
602b4a2924 r600: fix r600_draw_rectangle refcnt imbalance
The object buf is referenced at the beginning of the
r600_draw_rectangle() function and should be freed
at the end. This issue was introduced with cbb6e0277f.

Fixes: cbb6e0277f ("r600: stop using util_set_vertex_buffers")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 3b1e3a40a8)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:28 -07:00
Jose Maria Casanova Crespo
717e8a8caf v3d: mark FRAG_RESULT_COLOR as output_written on SAND blits FS
With the introduction of "v3d: Add support for 16bit normalised
formats" https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35820
nir_lower_fragcolor is always called if shaders outputs_written shows
that FRAG_RESULT_COLOR is used.

But on SAND8/30 blit fragment shaders although the FRAG_RESULT_COLOR
is used, it was not marked as output_written so the lowering was not
applied.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14141
Fixes: ee48e81b26 ("v3d: Always lower frag color")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit a131530dd1)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:27 -07:00
Emma Anholt
40ff53c5b8 wsi: Fix the flagging of dma_buf_sync_file for the amdgpu workaround.
In my regression fix, I covered one of the two paths that had stopped
setting the implicit_sync flag and thus triggered the amdgpu behavior we
don't want, but probably the less common one.

Fixes: f7cbc7b1c5 ("radv: Allocate BOs as implicit sync even if the WSI is doing implicit sync.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13942
(cherry picked from commit aa96444149)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:27 -07:00
Marek Olšák
bf9e1f2e37 winsys/radeon: fix completely broken tessellation for gfx6-7
The info was moved to radeon_info, but it was only set for the amdgpu
kernel driver. It was uninitialized for radeon.

Fixes: d82eda72a1 - ac/gpu_info: move HS info into radeon_info

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
(cherry picked from commit f5b648f6d3)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:26 -07:00
Benjamin Cheng
c3cf272a04 radv/video: Fill maxCodedExtent caps first
Later code (i.e. max qp map extent filling) depends on this.

Fixes: ae6ea69c85 ("radv: Implement VK_KHR_video_encode_quantization_map")
Reviewed-by: David Rosca <david.rosca@amd.com>
(cherry picked from commit b1370e1935)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:25 -07:00
Dylan Baker
30ba8880b4 .pick_status.json: Update to 28fbc6addb
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-21 14:42:24 -07:00
Job Noorman
42ab1c6f3c nir: mark fneg distribution through fadd/ffma as nsz
df1876f615 ("nir: Mark negative re-distribution on fadd as imprecise")
fixed the fadd case by marking it as imprecise. This commit fixes the
ffma case for the same reason.

However, "imprecise" isn't necessary and nowadays we have "nsz" which is
more accurate here. Use that for both fadd and ffma.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 62795475e8 ("nir/algebraic: Distribute source modifiers into instructions")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
(cherry picked from commit ad421cdf2e)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-17 07:41:30 -07:00
Josh Simmons
674e2a702a radv: Fix crash in sqtt due to uninitalized value
Fixes: 772b9ce411 ("radv: Remove qf from radv_spm/sqtt/perfcounter where applicable")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit b10c1a1952)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-17 07:41:29 -07:00
Mike Blumenkrantz
756618ee3b zink: consistently set/unset msrtss in begin_rendering
this has to always be set or unset, never persistent from previous renderpass

Fixes: 5080f2b6f5 ("zink: disable msrtss handling when blitting")
(cherry picked from commit f74cf45078)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-17 07:41:28 -07:00
Marek Olšák
ca7d2daf5f r300: fix DXTC blits
Fixes: 9d359c6d10 - gallium: delete pipe_surface::width and pipe_surface::height
(cherry picked from commit 733ba77bfe)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-17 07:41:27 -07:00
Xaver Hugl
45aafef631 vulkan/wsi: require extended target volume support for scRGB
It's hardly going to be useful without that

Signed-off-by: Xaver Hugl <xaver.hugl@kde.org>
Fixes: 4b663d56 ("vulkan/wsi: implement support for VK_EXT_hdr_metadata on Wayland")
(cherry picked from commit 892cf427a0)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-17 07:41:25 -07:00
Dylan Baker
8711394383 .pick_status.json: Mark c20e2733bf as denominated
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-17 07:41:23 -07:00
Dylan Baker
289c768e88 .pick_status.json: Update to ad421cdf2e
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-17 07:40:05 -07:00
Lionel Landwerlin
84655b4b5d anv: fix image-to-image copies of TileW images
The intermediate buffer between the 2 images is linear, its stride
should be a function of the tile's logical width.

Normally this should map to the values reported by ISL except for
TileW where for some reason it was decided to report 128 for TileW
instead of the actual 64 size (see isl_tiling_get_info() ISL_TILING_W
case)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
(cherry picked from commit 77fb8fb062)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-16 11:37:38 -07:00
Valentine Burley
fd6b9c70b6 docs: Update LAVA caching setup
After a recent change, `piglit-traces.sh` automatically sets the caching
proxy, so update the docs to reflect this.

Also update the name of the variable from `FDO_HTTP_CACHE_URI` to
`LAVA_HTTP_CACHE_URI`.

Fixes: fa74e939bf ("ci/piglit: automatically use LAVA proxy")

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
(cherry picked from commit 28e73a6239)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-16 11:37:37 -07:00
Lionel Landwerlin
9bb7bf9c66 Revert "wsi: Implements scaling controls for DRI3 presentation."
This reverts commit a219308867.

It's failing most of the tests on Anv :

$ ./deqp-vk -n dEQP-VK.wsi.xlib.maintenance1.scaling.*

Test run totals:
  Passed:        88/2422 (3.6%)
  Failed:        576/2422 (23.8%)
  Not supported: 1758/2422 (72.6%)
  Warnings:      0/2422 (0.0%)
  Waived:        0/2422 (0.0%)

The only passing tests seem to be with this pattern :

 dEQP-VK.wsi.xlib.maintenance1.scaling.*.same_size_and_aspect

(cherry picked from commit 2baa3b8c06)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-16 11:37:36 -07:00
Dylan Baker
f510e6a1bd .pick_status.json: Update to 3b2f7ed918
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38010>
2025-10-16 11:37:29 -07:00
Dylan Baker
40f7bef16c VERSION: bump for 25.3.0-rc1
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2025-10-15 20:56:25 -07:00
Faith Ekstrand
cb8cca0145 nvk: Expose cached and coherent as separate types on Tegra
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33959>
2025-10-15 23:03:19 -04:00
Faith Ekstrand
72c1c52b1d nvk/query: Handle non-coherent query pool memory
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33959>
2025-10-15 22:05:54 -04:00
Faith Ekstrand
35540f769d nvk/query: Rework query waits
Mostly, this is just a code restructure.  The two biggest changes are
that we now have one timeout for all query waits and that we wait for
all of them up-front instead of waiting per-query.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33959>
2025-10-15 22:05:54 -04:00
Faith Ekstrand
36fa755b19 nvk/query: Add an interleaved query layout
This gives us two options for how to layout queries.  One is optimized
for space while the other is optimized for safely touching from the CPU
with cached maps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33959>
2025-10-15 22:05:54 -04:00
Faith Ekstrand
65642d9e81 nvk/query: Add a vk_query_pool_report_count() helper
This lets us simplify a bit of the GetQueryPoolResults() code and make
it look more like the CL code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33959>
2025-10-15 22:05:54 -04:00
Faith Ekstrand
519c4c10f3 nvk/query: Pass an IS_TIMESTAMP flag explicitly to the CL kernel
This is more robust than looking at the report stride.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33959>
2025-10-15 22:05:54 -04:00